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Irie, Kanagawa
Go Irie, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090265170 | EMOTION DETECTING METHOD, EMOTION DETECTING APPARATUS, EMOTION DETECTING PROGRAM THAT IMPLEMENTS THE SAME METHOD, AND STORAGE MEDIUM THAT STORES THE SAME PROGRAM - An audio feature is extracted from audio signal data for each analysis frame and stored in a storage part. Then, the audio feature is read from the storage part, and an emotional state probability of the audio feature corresponding to an emotional state is calculated using one or more statistical models constructed based on previously input learning audio signal data. Then, based on the calculated emotional state probability, the emotional state of a section including the analysis frame is determined. | 10-22-2009 |
Kazuyuki Irie, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090032899 | Integrated circuit design based on scan design technology - An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another scan data line within the scan chain. The dummy block is configured to output data on the scan output terminal in response to input data fed to the scan input terminal, not responsively to the clock signal. | 02-05-2009 |
| 20100033229 | Clock gating circuit - Provided is a clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal. The clock gating circuit includes: a first latch that latches a signal value of the control signal in synchronization with the first clock signal; an AND that receives the first clock signal and controls an output of the second clock signal in response to an output signal of the first latch; and a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value. This enables execution of a scan test with a simple circuit configuration. | 02-11-2010 |
| 20100077271 | Method of achieving convergence of hold time error, device and program therefor - A method that achieves convergence of a hold time error in a relatively easy way without causing a setup time error even when the hold time error occurs in a large circuit, a device and a computer-readable storage medium storing a program therefor are provided. Group a first error path and a second error path in error paths which a hold time error occurs if there is a sharing path that shares its start point with the first error path and also shares its end point with the second error path, and insert a delay element without causing a setup time error per the grouped error paths. Convergence of a hold time error can be achieved without taking into account of a node that is not included in the group and there is no worry about causing a setup time error in a path that is not included in the group. | 03-25-2010 |
| 20110283248 | LAYOUT METHOD, LAYOUT SYSTEM, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING LAYOUT PROGRAM OF SEMICODUCTOR INTEGRATED CIRCUIT - A layout method of a semiconductor integrated circuit according to the present invention includes selecting M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from the same clock route; and replacing the M pieces of sequential circuits that are selected with one multi-data input/output sequential circuit including M pieces of input terminals and output terminals and one clock terminal that receives the clock distributed from the clock route. | 11-17-2011 |
Kenji Irie, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20080246581 | ELECTRONIC MACHINE, CONNECTED MACHINE IDENTIFYING METHOD FOR ELECTRONIC MACHINE AND CONTROL SYSTEM - An electronic machine connectable to a different apparatus is disclosed. The electronic machine includes a resistance, a connector to be connected to the different apparatus, and a detecting section that detects one state from multiple states based on the resistance value of the resistance and the resistance value of a resistance included in the different apparatus connected to the connector and controls multiple parameters based on the detected one state. | 10-09-2008 |
Masaki Irie, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20120045634 | Ceramics composite - The present invention relates to a ceramics composite including an inorganic material which includes: a matrix phase including a translucent ceramics; and a phosphor phase including YAG containing Ce, in which a content of the phosphor phase is from 22% by volume to 55% by volume based on the whole phase including the matrix phase and the phosphor phase, a content of Ce in the YAG is 0.005 to 0.05 in terms of an atomic ratio of Ce to Y (Ce/Y), and the ceramics composite has a thickness in a light outgoing direction of 30 μm to 200 μm. | 02-23-2012 |
Ryota Irie, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090066254 | SELF-BALLASTED FLUORESCENT LAMP AND LIGHTING APPARATUS - A self-ballasted fluorescent lamp capable of achieving a similar appearance to that of an electric light bulb for general illumination includes a base that is attached to a bottom end of a cover and a luminous tube that is supported at a top end of the cover. Electronic components forming a lighting circuit are mounted on a substrate. The substrate is formed to have such a width dimension that allows the substrate to be inserted into the base. The substrate is vertically disposed along a center axis of the base at a position offset from the center axis. Large electronic components are disposed on a first face of the substrate, which faces a large component area in the base formed by the offset substrate. | 03-12-2009 |
Takeshi Irie, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090041071 | CONTROL CIRCUIT FOR A LASER DIODE AND A METHOD TO CONTROL A LASER DIODE - A control circuit for a laser diode is disclosed, in which the driving current may be suppressed even when the monitor PD breaks down to make the APC feedback control inoperable. The control circuit comprises an LD driver to supply the driving current to the LD, a monitor PD to detect a portion of output light from the LD, and the APC controller to adjust the driving current. The current limiter, when the driving current reaches or exceeds the threshold, controls the driving current Id so as to keep the current in a preset value or a value just before the extraordinary increase of the driving current occurs. | 02-12-2009 |
Yasuyuki Irie, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090129781 | OPTICAL COMMUNICATION APPARATUS, OPTICAL COMMUNICATION METHOD, AND OPTICAL COMMUNICATION SYSTEM - Optical communication apparatuses capable of performing appropriate communication according to a distance to a receiving apparatus, optical communication methods, and an optical communication system are provided. A transmitting apparatus transmits an optical signal corresponding to data. The transmitting apparatus modulates intensity of the optical signal into intensity corresponding to a distance over which the data is to be delivered and outputs this intensity-modulated optical signal. This allows the transmitting apparatus to change the intensity of the optical signal corresponding to the data according to a distance to a receiving apparatus that receives the data, which thus allows the receiving apparatus to surely receive the data. | 05-21-2009 |
Yoshinobu Irie, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090212818 | Integrated circuit design method for improved testability - An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a flipflop-replaced netlist from the netlist. In classifying the flipflops, a flipflop which is connected to an input terminal of the macro directly or through an input-side logic cone and operated on the same clock signal as the macro is classified as a control type, and a flipflop which has a data output connected to an input terminal of the macro directly or through the input-side logic cone and operated on a different clock signal is classified as a hold type. In the flipflop-replaced netlist, the flipflop classified as the control type is replaced with a control flipflop which is configurable to toggle a data output thereof in synchronization with the clock signal by configuring a control input separately provided a data input thereof, and the flipflop classified as the hold type is replaced with a first hold flipflop which is configurable to hold data so that the data hold therein is unchanged. | 08-27-2009 |
Yosuke Irie, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090165274 | BALL BEARING MANUFACTURING FACILITY AND SUPER FINISH MACHINING APPARATUS - A detection unit of a matching apparatus | 07-02-2009 |