Patent application number | Description | Published |
20130042811 | Combinatorial Plasma Enhanced Deposition Techniques - Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate. | 02-21-2013 |
20130207105 | Controlled Localized Defect Paths for Resistive Memories - Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions. | 08-15-2013 |
20130209927 | Method and Apparatus For EUV Mask Having Diffusion Barrier - A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided. | 08-15-2013 |
20130214238 | Method for Forming Metal Oxides and Silicides in a Memory Device - Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process. | 08-22-2013 |
20130214240 | Memory Device with a Textured Lowered Electrode - Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack. | 08-22-2013 |
20130214808 | High Throughput Current-Voltage Combinatorial Characterization Tool and Method for Combinatorial Solar Test Substrates - Measuring current-voltage (I-V) characteristics of a solar cell using a lamp that emits light, a substrate that includes a plurality of solar cells, a positive electrode attached to the solar cells, and a negative electrode peripherally deposited around each of the solar cells and connected to a common ground, an articulation platform coupled to the substrate, a multi-probe switching matrix or a Z-stage device, a programmable switch box coupled to the multi-probe switching matrix or Z-stage device and selectively articulating the probes by raising the probes until in contact with at least one of the positive electrode and the negative electrode and lowering the probes until contact is lost with at least one of the positive electrode and the negative electrode, a source meter coupled to the programmable switch box and measuring the I-V characteristics of the substrate. | 08-22-2013 |
20130217179 | Nonvolatile Memory Device Having An Electrode Interface Coupling Region - Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another. | 08-22-2013 |
20130217200 | Resistive-Switching Nonvolatile Memory Elements - Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer. | 08-22-2013 |
20130217202 | HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. | 08-22-2013 |
20130217238 | Substrate Processing Including A Masking Layer - Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer. | 08-22-2013 |
20130221314 | Memory Device Having An Integrated Two-Terminal Current Limiting Resistor - A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 08-29-2013 |
20130221315 | Memory Cell Having an Integrated Two-Terminal Current Limiting Resistor - A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 08-29-2013 |
20130285159 | METHOD FOR ETCHING GATE STACK - A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack. | 10-31-2013 |
20130323863 | Method for Generating Graphene Structures - A method for depositing graphene is provided. The method includes depositing a layer of non-conducting amorphous carbon over a surface of a substrate and depositing a transition metal in a pattern over the amorphous carbon. The substrate is annealed at a temperature below 500° C., where the annealing converts the non-conducting amorphous carbon disposed under the transition metal to conducting amorphous carbon. A portion of the pattern of the transition metal is removed from the surface of the substrate to expose the conducting amorphous carbon. | 12-05-2013 |
20140080250 | Method of Fabricating High Efficiency CIGS Solar Cells - A method is disclosed for fabricating high efficiency CIGS solar cells including the deposition of a multi-component metal precursor film on a substrate. The substrate is then inserted into a system suitable for exposing the precursor to a chalcogen to form a chalcogenide TFPV absorber. One or more Na precursors are used to deposit a Na-containing layer on the precursor film in the system. This method eliminates the use of dedicated equipment and processes for introducing Na to the TFPV absorber. | 03-20-2014 |
20140080322 | Emissivity Profile Control for Thermal Uniformity - A substrate for processing in a heating system is disclosed. The substrate includes a bottom portion for absorbing heat from a radiating heat source, the bottom portion having a first region having a first emissivity and a second region having a second emissivity less than the first emissivity. The first region and the second region promote thermal uniformity of the substrate by compensating for thermal non-uniformity of the radiating heat source. | 03-20-2014 |
20140117303 | Resistive Random Access Memory Cells Having METAL ALLOY Current Limiting layers - Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance. | 05-01-2014 |
20140166960 | IL-Free MIM stack for clean RRAM Devices - A nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, and methods of forming the same. A nonvolatile memory element includes a first electrode layer formed on a substrate, a resistive switching layer formed on the first electrode layer, and a second electrode layer. The resistive switching layer comprises a metal oxide and is disposed between the first electrode layer and the second electrode layer. The elemental metal selected for each of the first and second electrode layers is the same metal as selected to form the metal oxide resistive switching layer. The use of common metal materials within the memory element eliminates the growth of unwanted and incompatible native oxide interfacial layers that create undesirable circuit impedance. | 06-19-2014 |
20140175360 | Bilayered Oxide Structures for ReRAM Cells - Provided are resistive random access memory (ReRAM) cells having bi-layered metal oxide structures. The layers of a bi-layered structure may have different compositions and thicknesses. Specifically, one layer may be thinner than the other layer, sometimes as much as 5 to 20 times thinner. The thinner layer may be less than 30 Angstroms thick or even less than 10 Angstroms thick. The thinner layer is generally more oxygen rich than the thicker layer. Oxygen deficiency of the thinner layer may be less than 5 atomic percent or even less than 2 atomic percent. In some embodiments, a highest oxidation state metal oxide may be used to form a thinner layer. The thinner layer typically directly interfaces with one of the electrodes, such as an electrode made from doped polysilicon. Combining these specifically configured layers into the bi-layered structure allows improving forming and operating characteristics of ReRAM cells. | 06-26-2014 |
20140175362 | Limited Maximum Fields of Electrode-Switching Layer Interfaces in Re-RAM Cells - Provided are ReRAM cells, each having at least one interface between an electrode and a resistive switching layers with a maximum field value of less than 0.25. The electrode materials forming such interfaces include tantalum nitrides doped with lanthanum, aluminum, erbium yttrium, or terbium (e.g., Ta | 06-26-2014 |
20140175364 | RADIATION ENHANCED RESISTIVE SWITCHING LAYERS - Provided are radiation enhanced resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming these layers and cells. Radiation creates defects in resistive switching materials that allow forming and breaking conductive paths in these materials thereby improving their resistive switching characteristics. For example, ionizing radiation may break chemical bonds in various materials used for such a layer, while non-ionizing radiation may form electronic traps. Radiation power, dozing, and other processing characteristics can be controlled to generate a distribution of defects within the resistive switching layer. For example, an uneven distribution of defects through the thickness of a layer may help with lowering switching voltages and/or currents. Radiation may be performed before or after thermal annealing, which may be used to control distribution of radiation created defects and other types of defects in resistive switching layers. | 06-26-2014 |
20140175618 | TRANSITION METAL ALUMINATE AND HIGH K DIELECTRIC SEMICONDUCTOR STACK - Methods of forming a high K dielectric semiconductor stack are described. A semiconductor substrate is provided, in which the native oxide layer is removed. A transition metal aluminate layer is deposited onto the semiconductor substrate across discrete multiple regions in a combinatorial manner. A high K dielectric layer is deposited onto the transition metal aluminate layer across the discrete multiple regions in a combinatorial manner. The transition metal aluminate layer and the high K dielectric layer are patterned to form a plurality of high K dielectric semiconductor stacks across discrete multiple regions. A three-five semiconductor substrate or a germanium substrate can be used in methods of forming a high K dielectric semiconductor stack. | 06-26-2014 |
20140179112 | High Productivity Combinatorial Techniques for Titanium Nitride Etching - Provided are methods of High Productivity Combinatorial testing of semiconductor substrates, each including multiple site isolated regions. Each site isolated region includes a titanium nitride structure as well as a hafnium oxide structure and/or a polysilicon structure. Each site isolated region is exposed to an etching solution that includes sulfuric acid, hydrogen peroxide, and hydrogen fluoride. The composition of the etching solution and/or etching conditions are varied among the site isolated regions to study effects of this variation on the etching selectivity of titanium nitride relative to hafnium oxide and/or polysilicon and on the etching rates. The concentration of sulfuric acid and/or hydrogen peroxide in the etching solution may be less than 7% by volume each, while the concentration of hydrogen fluoride may be between 50 ppm and 200 ppm. In some embodiments, the temperature of the etching solution is maintained at between about 40° C. and 60° C. | 06-26-2014 |
20140185034 | Method to Extend Single Wavelength Ellipsometer to Obtain Spectra of Refractive Index - Methods are provided to use data obtained from a single wavelength ellipsometer to determine the refractive index of materials as a function of wavelength for thin conductive films. The methods may be used to calculate the refractive index spectrum as a function of wavelength for thin films of metals, and conductive materials such as conductive metal nitrides or conductive metal oxides. | 07-03-2014 |
20140186598 | Base-layer consisting of two materials layer with extreme high/low index in low-e coating to improve the neutral color and transmittance performance - Low emissivity coated panels can be fabricated using a base layer having a low refractive index layer on a high refractive index layer. The low refractive index layer can have refractive index less than 1.5, and can include Mg F | 07-03-2014 |
20140187041 | High Dose Ion-Implanted Photoresist Removal Using Organic Solvent and Transition Metal Mixtures - Provided are methods for processing semiconductor substrates to remove high-dose ion implanted (HDI) photoresist structures without damaging other structures made of titanium nitride, tantalum nitride, hafnium oxide, and/or hafnium silicon oxide. The removal is performed using a mixture of an organic solvent, an oxidant, a metal-based catalyst, and one of a base or an acid. Some examples of suitable organic solvents include dimethyl sulfoxide, n-ethyl pyrrolidone, monomethyl ether, and ethyl lactate. Transition metals in their zero-oxidation state, such as metallic iron or metallic chromium, may be used as catalysts in this mixture. In some embodiments, a mixture includes ethyl lactate, of tetra-methyl ammonium hydroxide, and less than 1% by weight of the metal-based catalyst. The etching rate of the HDI photoresist may be at least about 100 Angstroms per minute, while other structures may remain substantially intact. | 07-03-2014 |
20140187051 | Poly Removal for replacement gate with an APM mixture - A method for removing poly-silicon dummy gate structures using an ammonium hydroxide-hydrogen peroxide-water (APM) solution with concentrations between 1:10:20 and 1:1:2 and at temperatures between 20 C and 80 C for times between 1 minute and 60 minutes. | 07-03-2014 |
20140264492 | COUNTER-DOPED LOW-POWER FINFET - FinFETs and methods for making FinFETs are disclosed. A fin is formed on a substrate, wherein the fin has a height greater than 2 to 6 times of its width, a length defining a channel between source and drain ends, and the fin comprises a lightly doped semiconductor. A conformally doped region of counter-doped semiconductor is formed on the fin using methods such as monolayer doping, sacrificial oxide doping, or low energy plasma doping. Halo-doped regions are formed by angled ion implantation. The halo-doped regions are disposed in the lower portion of the source and drain and adjacent to the fin. Energy band barrier regions can be formed at the edges of the halo-doped regions by angled ion implantation. | 09-18-2014 |
20140264634 | FINFET FOR RF AND ANALOG INTEGRATED CIRCUITS - Methods for making a FinFET having reduced device mismatch and low-frequency noise are disclosed for RF/analog IC designs. A semiconductor fin is formed having a height between 2 and 6 times its width, atomically smooth sidewalls, and rounded active corners to minimize device variability. The fin is operable as a channel between a source and a drain. A first layer of SiO | 09-18-2014 |
20140272335 | Low-E Glazing Performance by Seed Structure Optimization - A bi-layer seed layer can exhibit good seed property for an infrared reflective layer, together with improved thermal stability. The bi-layer seed layer can include a thin zinc oxide layer having a desired crystallographic orientation for a silver infrared reflective layer disposed on a bottom layer having a desired thermal stability. The thermal stable layer can include aluminum, magnesium, or bismuth doped tin oxide (AlSnO, MgSnO, or BiSnO), which can have better thermal stability than zinc oxide but poorer lattice matching for serving as a seed layer template for silver (111). | 09-18-2014 |