Patent application number | Description | Published |
20080225426 | Magnetic recording device including a thermal proximity sensor - A system includes a magnetic device for writing to and reading from a magnetic medium and a sensor disposed adjacent to the magnetic device and proximate to the magnetic medium. The sensor generates signals related to thermal variations in the sensor caused by changes in a distance between the magnetic device and the magnetic medium. | 09-18-2008 |
20090184930 | POSITION DETECTING DISPLAY PANEL - An array of sensors, which is coupled to an array of pixel elements in a position detecting display panel, includes sensors that are each registered with a corresponding pixel element of the array of pixel elements, and that each include a material exhibiting magneto-electric behavior in response to a magnetic field source. Some systems may include the position detecting display panel and at least one separate stylus, which includes the magnetic field source. A voltage source, that is operably coupled to each sensor and each pixel element, applies a voltage across one or more particular pixel elements, according to the magneto-electric behavior of the corresponding sensor(s), when the magnetic field source is brought into proximity the corresponding sensor(s). | 07-23-2009 |
20090268352 | ST-RAM MAGNETIC ELEMENT CONFIGURATIONS TO REDUCE SWITCHING CURRENT - In order to increase an efficiency of spin transfer and thereby reduce the required switching current, a current perpendicular to plane (CPP) magnetic element for a memory device includes either one or both of a free magnetic layer, which has an electronically reflective surface, and a permanent magnet layer, which has perpendicular anisotropy to bias the free magnetic layer. | 10-29-2009 |
20090283816 | BAND ENGINEERED HIGH-K TUNNEL OXIDES FOR NON-VOLATILE MEMORY - A non-volatile memory cell that has a charge source region, a charge storage region, and a crested tunnel barrier layer that has a potential energy profile which peaks between the charge source region and the charge storage region. The tunnel barrier layer has multiple high-K dielectric materials, either as individual layers or as compositionally graded materials. | 11-19-2009 |
20090289736 | MAGNETIC SWITCHES FOR SPINWAVE TRANSMISSION - Spinwave transmission systems that include switching devices to direct the transmission of the spinwaves used for data transfer and processing. In one particular embodiment, a system for spinwave transmission has a first magnetic stripe configured for transmission of a spinwave and a second magnetic stripe for transmission of the spinwave, with a gap therebetween. The system includes a coupler that has a first orientation and a second orientation, where in the first orientation, no magnetic connection is made between the magnetic stripes, and in the second orientation, a connection is made between the magnetic stripes. The connection allows transmission of the spinwave from the first magnetic stripe to the second magnetic stripe. The first and second orientation may be the physical position of the coupler, moved by thermal, piezoelectric, or electrostatic forces, or, the first and second orientation may be a magnetic state of the coupler. | 11-26-2009 |
20090303076 | WIRELESS AND BATTERY-LESS MONITORING UNIT - A wireless and battery-less sensor device is described. The sensor device includes a mechanical energy harvesting device, a sensor electrically coupled to the mechanical energy harvesting module. The sensor is configured to sense with the power supplied by the mechanical energy harvesting device. Nonvolatile memory is configured to store output from the sensor. A radio frequency energy harvesting module is electrically coupled to a radio frequency transmitter. The radio frequency transmitter is configured to transmit the output from the sensor with the power supplied by the radio frequency energy harvesting device. Systems and methods utilizing the wireless and battery-less sensor device are also described. | 12-10-2009 |
20090315088 | FERROELECTRIC MEMORY USING MULTIFERROICS - Ferroelectric memory using multiferroics is described. The multiferrroic memory includes a substrate having a source region, a drain region and a channel region separating the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A data storage cell having a composite multiferroic layer is adjacent to the electrically insulating layer. The electrically insulating layer separated the data storage cell form the channel region. A control gate electrode is adjacent to the data storage cell. The data storage cell separates at least a portion of the control gate electrode from the electrically insulating layer. | 12-24-2009 |
20100032636 | NON-VOLATILE MEMORY CELL WITH ENHANCED FILAMENT FORMATION CHARACTERISTICS - Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode. | 02-11-2010 |
20100032778 | MAGNETIC MEMORY WITH SEPARATE READ AND WRITE PATHS - Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction. | 02-11-2010 |
20100034008 | MAGNETIC FIELD ASSISTED STRAM CELLS - Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a current through the magnetic tunnel junction cell, the spin torque current source having a direction perpendicular to the magnetization orientations, and also includes a magnetic ampere field current source is oriented in a direction orthogonal or at some angles to the magnetization orientations. | 02-11-2010 |
20100038735 | MAGNET-ASSISTED TRANSISTOR DEVICES - A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device. | 02-18-2010 |
20100039105 | MAGNETIC OSCILLATOR BASED BIOSENSOR - A biosensor is described. The biosensor includes a fixed multilayer stack providing a magnetization oscillation, a voltage source electrically coupled to the fixed multilayer stack, and a binding molecule covalently bonded to the biosensor. The voltage source provides a direct current through the fixed multilayer stack to generate the magnetization oscillation and a target molecule including a magnetic nanoparticle forms a complex with the binding molecule and alters the magnetization oscillation. | 02-18-2010 |
20100084724 | MEMORY CELL WITH STRESS-INDUCED ANISOTROPY - A magnetic memory element that has a stress-induced magnetic anisotropy. The memory element has a ferromagnetic free layer having a switchable magnetization orientation switchable, a ferromagnetic reference layer having a pinned magnetization orientation, and a non-magnetic spacer layer therebetween. The free layer may be circular, essentially circular or nearly circular. | 04-08-2010 |
20100102289 | NONVOLATILE RESISTIVE MEMORY DEVICES - Nonvolatile resistive memory devices are disclosed. In some embodiments, the memory devices comprise multilayer structures including electrodes, one or more resistive storage layers, and separation layers. The separation layers insulate the resistive storage layers to prevent charge leakage from the storage layers and allow for the use of thin resistive storage layers. In some embodiments, the nonvolatile resistive memory device includes a metallic multilayer comprising two metallic layers about an interlayer. A dopant at an interface of the interlayer and metallic layers can provide a switchable electric field within the multilayer. | 04-29-2010 |
20100102308 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH OXIDE LAYER - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode. | 04-29-2010 |
20100102369 | FERROELECTRIC MEMORY WITH MAGNETOELECTRIC ELEMENT - A ferroelectric memory cell that has a magnetoelectric element between a first electrode and a second electrode, the magnetoelectric element comprising a ferromagnetic material layer and a multiferroic material layer with an interface therebetween. The magnetization orientation of the ferromagnetic material layer and the multiferroic material layer may be in-plane or out-of-plane. FeRAM memory devices are also provided. | 04-29-2010 |
20100102406 | MAGNETIC STACK DESIGN - A magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween. The stack includes an annular antiferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer. In some embodiments, the reference layer is larger than the free layer. | 04-29-2010 |
20100104115 | MICRO MAGNETIC SPEAKER DEVICE WITH BALANCED MEMBRANE - A micro magnetic device with a micro magnetic speaker unit having a first element, a second element, and a membrane therebetween. Each of the elements comprises a body, a pole of soft magnetic material, an electrically conductive coil positioned around the pole, and a permanent magnet connected to the membrane. The first element and the second element are magnetically identical. A plurality of speaker units can be combined to provide a speaker array. | 04-29-2010 |
20100108975 | NON-VOLATILE MEMORY CELL FORMATION - A method and apparatus for forming a non-volatile memory cell, such as a PMC memory cell. In some embodiments, a first electrode is connected to a source while a second electrode is connected to a ground. An ionic region is located between the first and second electrodes and comprises a doping layer, composite layer, and electrolyte layer. The composite layer has a low resistive state and the electrolyte layer switches from a high resistive state to a low resistive state based on the presence of a filament. | 05-06-2010 |
20100110746 | MEMORY CELL WITH ALIGNMENT STRUCTURE - A memory cell that includes a memory element configured for switching from a first data state to a second data state by passage of current therethrough. The memory cell includes a top electrode and a bottom electrode for providing the current through the memory cell, and an alignment element positioned at least between the top electrode and the top surface of the memory element, the alignment element having an electrically conductive body tapering from the top electrode to the top surface of the memory element. Methods for forming the memory cell are also described. | 05-06-2010 |
20100110759 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH FILAMENT PLACEMENT STRUCTURE - Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm. | 05-06-2010 |
20100110764 | PROGRAMMABLE METALLIZATION CELL SWITCH AND MEMORY UNITS CONTAINING THE SAME - An electronic device that includes a first programmable metallization cell (PMC) that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode; and a second PMC that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode, wherein the first and second PMCs are electrically connected in anti-parallel. | 05-06-2010 |
20100110765 | Non-Volatile Memory Cell with Programmable Unipolar Switching Element - A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element. | 05-06-2010 |
20100117051 | MEMORY CELLS INCLUDING NANOPOROUS LAYERS CONTAINING CONDUCTIVE MATERIAL - A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer. | 05-13-2010 |
20100123210 | ASYMMETRIC BARRIER DIODE - A diode having a reference voltage electrode, a variable voltage electrode, and a diode material between the electrodes. The diode material is formed of at least one high-K dielectric material and has an asymmetric energy barrier between the reference voltage electrode and the variable voltage electrode, with the energy barrier having a relatively maximum energy barrier level proximate the reference voltage electrode and a minimum energy barrier level proximate the variable voltage electrode. | 05-20-2010 |
20100123542 | NANO-DIMENSIONAL NON-VOLATILE MEMORY CELLS - A non-volatile memory cell that includes a first electrode; a second electrode; and an electrical contact region that electrically connects the first electrode and the second electrode, the electrical contact region has a end portion and a continuous side portion, and together, the end portion and the continuous side portion form an open cavity, wherein the memory cell has a high resistance state and a low resistance state that can be switched by applying a voltage across the first electrode and the second electrode. | 05-20-2010 |
20100124106 | MAGNETIC MEMORY WITH MAGNETIC TUNNEL JUNCTION CELL SETS - A memory apparatus having at least one memory cell set comprising a first spin torque memory cell electrically connected in series to a second spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The memory cell set itself is configured to switch between a high resistance state and a low resistance state. The memory apparatus also has at least one reference cell set comprising a third spin torque memory cell electrically connected in anti-series to a fourth spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The reference cell set itself has a reference resistance that is a midpoint of the high resistance state and the low resistance state of the memory cell set. | 05-20-2010 |
20100124352 | MICRO MAGNETIC DEVICE WITH MAGNETIC SPRING - A micro magnetic device having a body defining at least part of an enclosed chamber, the body comprising a first sidewall and a second sidewall. A pole comprising a soft magnetic material is within the chamber and an electrically conductive coil is positioned around the pole. A diaphragm is connected to the first sidewall and a permanent dipole magnet is connected to the second sidewall at a first end and to the diaphragm at a second end. The dipole magnet is offset centrally from the pole. The diaphragm may also be offset centrally from the first pole. The micro magnetic device may be made by MEMS or thin film techniques. | 05-20-2010 |
20100135061 | Non-Volatile Memory Cell with Ferroelectric Layer Configurations - In some embodiments of the invention a non-volatile memory cell is provided with a first electrode, a second electrode, and one or more side layers of a ferroelectric metal oxide and a ferroelectric material layer between the first and second electrodes. The ferroelectric material layer may be provided between, e.g., adjacent, two side layers of a ferroelectric metal oxide or between a single layer of a ferroelectric metal oxide and an electrode. The ferroelectric metal oxide may in some cases include a uniform layered structure such as a bismuth layer-structured ferroelectric material like Bi | 06-03-2010 |
20100182837 | MAGNETIC FLOATING GATE MEMORY - An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element. | 07-22-2010 |
20100193761 | PROGRAMMABLE METALLIZATION MEMORY CELL WITH LAYERED SOLID ELECTROLYTE STRUCTURE - Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed. | 08-05-2010 |
20100207219 | SINGLE LINE MRAM - A magnetic memory device includes a first electrode separated from a second electrode by a magnetic tunnel junction. The first electrode provides a write current path along a length of the first electrode. The magnetic tunnel junction includes a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation. The free magnetic layer is spaced from the first electrode a distance of less than 10 nanometers. A current passing along the write current path generates a magnetic field. The magnetic field switches the free magnetic layer magnetization orientation between a high resistance state magnetization orientation and a low resistance state magnetization orientation. | 08-19-2010 |
20100220512 | PROGRAMMABLE POWER SOURCE USING ARRAY OF RESISTIVE SENSE MEMORY CELLS - Various embodiments of the present invention are generally directed to an apparatus comprising a programmable power source which uses an array of resistive sense memory cells, such as but not limited to STRAM or RRAM cells, to provide a controlled power bias to a load, such as but not limited to a micro-oscillator. In some embodiments, the programmable power source incorporates an array of serially connected resistive sense memory cells. A selectively controllable power level is applied by the programmable power source to a load in relation to a control input which selectively programs at least selected ones of the memory cells to a selected resistance state. | 09-02-2010 |
20100277969 | STRUCTURES FOR RESISTIVE RANDOM ACCESS MEMORY CELLS - A resistive random access memory (RRAM) cell that includes a first electrode having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; a resistive layer having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; and a second electrode having a lower portion, an upper portion and an outer surface; wherein the outer surface of the resistive layer directly contacts the inner surface of the first electrode. | 11-04-2010 |
20110002161 | PHASE CHANGE MEMORY CELL WITH SELECTING ELEMENT - A memory cell comprising a phase-change memory cell stacked in series with a resistive switch. The resistive switch has a material switchable between a high resistance state and a low resistance state by the application of a voltage. A plurality of memory cells are used to form a memory array. | 01-06-2011 |
20110006276 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 01-13-2011 |
20110007544 | Non-Volatile Memory with Active Ionic Interface Region - A non-volatile memory cell and method of use therefore are disclosed. In accordance with various embodiments, the memory cell comprises a tunneling region disposed between a conducting region and a metal region, wherein the tunneling region comprises an active interface region disposed between a first tunneling barrier and a second tunneling barrier. A high resistive film is formed in the active interface region with migration of ions from both the metal and conducting regions responsive to a write current to program the memory cell to a selected resistive state. | 01-13-2011 |
20110007545 | Non-Volatile Memory Cell Stack with Dual Resistive Elements - A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element. | 01-13-2011 |
20110007546 | Anti-Parallel Diode Structure and Method of Fabrication - An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region. | 01-13-2011 |
20110007548 | Hierarchical Cross-Point Array of Non-Volatile Memory - A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells. | 01-13-2011 |
20110007551 | Non-Volatile Memory Cell with Non-Ohmic Selection Layer - A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold. | 01-13-2011 |
20110007581 | Current Cancellation for Non-Volatile Memory - A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current. | 01-13-2011 |
20110089509 | MAGNETIC MEMORY WITH SEPARATE READ AND WRITE PATHS - Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction. | 04-21-2011 |
20110117717 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH FILAMENT PLACEMENT STRUCTURE - Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm. | 05-19-2011 |
20110121256 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH FILAMENT PLACEMENT STRUCTURE - Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm. | 05-26-2011 |
20110122678 | Anti-Parallel Diode Structure and Method of Fabrication - An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region. | 05-26-2011 |
20110180888 | MAGNETIC STACK DESIGN - A magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween. The stack includes an annular antiferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer. In some embodiments, the reference layer is larger than the free layer. | 07-28-2011 |
20110182106 | Current Cancellation for Non-Volatile Memory - A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current. | 07-28-2011 |
20110188293 | Non-Volatile Memory Cell With Non-Ohmic Selection Layer - A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold. | 08-04-2011 |
20110193148 | MAGNET-ASSISTED TRANSISTOR DEVICES - A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device. | 08-11-2011 |
20110199832 | MAGNETIC FLOATING GATE MEMORY - An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element. | 08-18-2011 |
20110228599 | Non-Volatile Memory Cell with Programmable Unipolar Switching Element - A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element. | 09-22-2011 |
20110254113 | ST-RAM MAGNETIC ELEMENT CONFIGURATIONS TO REDUCE SWITCHING CURRENT - In order to increase an efficiency of spin transfer and thereby reduce the required switching current, a current perpendicular to plane (CPP) magnetic element for a memory device includes either one or both of a free magnetic layer, which has an electronically reflective surface, and a permanent magnet layer, which has perpendicular anisotropy to bias the free magnetic layer. | 10-20-2011 |
20110300687 | NANO-DIMENSIONAL NON-VOLATILE MEMORY CELLS - A non-volatile memory cell that includes a first electrode; a second electrode; and an electrical contact region that electrically connects the first electrode and the second electrode, the electrical contact region has a end portion and a continuous side portion, and together, the end portion and the continuous side portion form an open cavity, wherein the memory cell has a high resistance state and a low resistance state that can be switched by applying a voltage across the first electrode and the second electrode. | 12-08-2011 |
20120032131 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH OXIDE LAYER - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode. | 02-09-2012 |
20120039112 | Hierarchical Cross-Point Array of Non-Volatile Memory - A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells. | 02-16-2012 |
20120040496 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH OXIDE LAYER - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode. | 02-16-2012 |
20120149183 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 06-14-2012 |
20120199936 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 08-09-2012 |
20120250405 | MAGNETIC FIELD ASSISTED STRAM CELLS - Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a current through the magnetic tunnel junction cell, the spin torque current source having a direction perpendicular to the magnetization orientations, and also includes a magnetic ampere field current source is oriented in a direction orthogonal or at some angles to the magnetization orientations. | 10-04-2012 |
20130330901 | PROGRAMMABLE METALLIZATION MEMORY CELL WITH LAYERED SOLID ELECTROLYTE STRUCTURE - Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed. | 12-12-2013 |
20140015075 | MAGNETIC MEMORY WITH SEPARATE READ AND WRITE PATHS - Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction. | 01-16-2014 |