Patent application number | Description | Published |
20120086074 | Semiconductor Devices And Methods of Forming The Same - Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include a trench in a substrate. The semiconductor devices may also include a bulk electrode within opposing sidewalls of the trench. The semiconductor devices may further include a liner electrode between the bulk electrode and the opposing sidewalls of the trench. The liner electrode may include a sidewall portion between a sidewall of the bulk electrode and one of the opposing sidewalls of the trench. | 04-12-2012 |
20120126300 | CAPACITORS, SEMICONDUCTOR DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES - A capacitor includes a first electrode, a first dielectric layer disposed on the first electrode, the first dielectric layer having a tetragonal crystal structure and including a first metal oxide layer doped with a first impurity, a second dielectric layer disposed on the first metal oxide layer, the second dielectric layer having a tetragonal crystal structure and including a second metal oxide layer doped with a second impurity, and a second electrode disposed on the second dielectric layer. The first dielectric layer has a lower crystallization temperature and a substantially higher dielectric constant than the second dielectric layer. | 05-24-2012 |
20120171837 | Semiconductor Memory Devices And Methods Of Fabricating The Same - Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a plurality of spaces, treating the plurality of diode patterns to form a plurality of semiconductor patterns in each of the plurality of spaces, removing portions of the plurality of semiconductor patterns to form a recess in each of the plurality of spaces, treating the of the plurality of semiconductor patterns to form a plurality of diodes in each of the plurality of spaces, forming a bottom electrode on each of the plurality of diodes, forming a plurality of memory elements on each of the bottom electrodes, and forming a plurality of upper interconnection lines on the plurality of memory elements. | 07-05-2012 |
20140131655 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a plurality of spaces, treating the plurality of diode patterns to form a plurality of semiconductor patterns in each of the plurality of spaces, removing portions of the plurality of semiconductor patterns to form a recess in each of the plurality of spaces, treating the of the plurality of semiconductor patterns to form a plurality of diodes in each of the plurality of spaces, forming a bottom electrode on each of the plurality of diodes, forming a plurality of memory elements on each of the bottom electrodes, and forming a plurality of upper interconnection lines on the plurality of memory elements. | 05-15-2014 |
20140183434 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF FORMING THE SAME - Semiconductor devices, and methods of fabricating the same, include a metal-containing layer on a semiconductor layer, and a barrier-lowering portion between the metal-containing layer and the semiconductor layer. The barrier-lowering portion lowers a Schottky barrier height between the metal-containing layer and the semiconductor layer below a Schottky barrier height between a metal silicide layer and the semiconductor layer. | 07-03-2014 |
20140264517 | SEMICONDUCTOR DEVICES HAVING A SILICON-GERMANIUM CHANNEL LAYER AND METHODS OF FORMING THE SAME - Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature. | 09-18-2014 |