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Inns
Daniel Inns, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110212622 | SURFACE TEXTURING USING A LOW QUALITY DIELECTRIC LAYER - A low cost method is described for forming a textured Si surface such as for a solar cell which includes forming a dielectric layer containing pinholes, anisotropically etching through the pinholes to form inverted pyramids in the Si surface and removing the dielectric layer thereby producing a high light trapping efficiency for incident radiation. | 09-01-2011 |
Daniel A. Inns, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100221867 | LOW COST SOI SUBSTRATES FOR MONOLITHIC SOLAR CELLS - A lost cost method for fabricating SOI substrates is provided. The method includes forming a stack of p-type doped amorphous Si-containing layers on a semiconductor region of a substrate by utilizing an evaporation deposition process. A solid phase recrystallization step is then performed to convert the amorphous Si-containing layers within the stack into a stack of p-type doped single crystalline Si-containing layers. After recrystallization, the single crystalline Si-containing layers are subjected to anodization and at least an oxidation step to form an SOI substrate. Solar cells and/or other semiconductor devices can be formed on the upper surface of the inventive SOI substrate. | 09-02-2010 |
| 20110162702 | QUASI-PYRAMIDAL TEXTURED SURFACES USING PHASE-SEGREGATED MASKS - A method of texturing a surface of a substrate utilizing a phase-segregated mask and etching is disclosed. The resulting textured surface, which can be used as a component of a solar cell includes, in one embodiment, a randomly mixed collection of flat-topped and angled surfaces providing local high points and local low points. The flat-topped surfaces have an areal density of at least 1%, and the high points are coincident with the flat-topped surfaces. Moreover, a preponderance of said low points are approximately situated in a single common plane parallel to the plane defined by the flat-topped surfaces. | 07-07-2011 |
Daniel A. Inns, White Plains, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100035409 | CRYSTALLINE SILICON SUBSTRATES WITH IMPROVED MINORITY CARRIER LIFETIME - A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200° C. or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl. | 02-11-2010 |
| 20100112792 | THICK EPITAXIAL SILICON BY GRAIN REORIENTATION ANNEALING AND APPLICATIONS THEREOF - The invention provides a high temperature (about 1150° C. or greater) annealing process for converting thick polycrystalline Si layers on the order of 1 μm to 40 μm on a single crystal seed layer into thick single crystal Si layers having the orientation of the seed layer, thus allowing production of thick Si films having the quality of single crystal silicon at high rates and low cost of processing. Methods of integrating such high temperature processing into solar cell fabrication are described, with particular attention to process flows in which the seed layer is disposed on a porous silicon release layer. Another aspect pertains to the use of similar high temperature anneals for poly-Si grain growth and grain boundary passivation. A further aspect relates to structures in which these thick single crystal Si films and passivated poly-Si films are incorporated. | 05-06-2010 |
Daniel A. Inns, New South Wales AU
| Patent application number | Description | Published |
|---|---|---|
| 20080276986 | Photolithography Method For Contacting Thin-Film Semiconductor Structures - A photolithography method for contacting one or more contact regions of a thin-film semiconductor structure on a transparent supporting material is disclosed. The method comprises the steps of forming one or more openings ( | 11-13-2008 |
Daniel A. Inns, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120031476 | COMPOSITIONALLY-GRADED BAND GAP HETEROJUNCTION SOLAR CELL - A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device. | 02-09-2012 |
Martyn Inns, Gloucester GB
| Patent application number | Description | Published |
|---|---|---|
| 20100257946 | LOAD INDICATOR - A load indicator comprises a load bearing assembly of first and second load bearing members ( | 10-14-2010 |