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In-Sang
In-Sang Jeom, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080305620 | METHODS OF FORMING DEVICES INCLUDING DIFFERENT GATE INSULATING LAYERS ON PMOS/NMOS REGIONS - Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer. | 12-11-2008 |
In-Sang Jeon, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090134448 | Non-volatile memory device and method of forming the same - Example embodiments provide a non-volatile semiconductor memory device and method of forming the same. The non-volatile memory device may include a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a first blocking insulation layer on the charge storage layer, and a gate electrode on the first blocking insulation layer, wherein the gate electrode includes aluminum and the first blocking insulation layer does not include aluminum. | 05-28-2009 |
| 20100213541 | SEMICONDUCTOR DEVICE HAVING RECESS CHANNEL STRUCTURE - An integrated circuit device includes a semiconductor substrate including an active region defined by an isolation region and having at least one trench therein, a gate insulating layer formed in the at least one trench, a gate electrode layer having a nano-crystalline structure disposed on the gate insulating layer and a word line on the gate electrode layer in the at least one trench. The device may further include a capping layer on the word line. | 08-26-2010 |
| 20100240180 | Methods of Manufacturing Semiconductor Devices Having Low Resistance Buried Gate Structures - In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern. | 09-23-2010 |
In-Sang Kim, Whasung-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110139030 | LARGE RIDEABLE BIPEDAL WALKING ROBOT FOR USE AS AN AMUSEMENT PARK RIDE AND AMUSEMENT PARK SYSTEM USING THE SAME - A large bipedal walking robot that a human can directly board and ride and that may be used as an amusement park ride, and to an amusement park system using the same includes a large bipedal walking robot capable of being boarded and ridden, a boarding vehicle to be coupled to the head or body of the robot, a safety cable and a safety rail that prevent the robot from falling, a safety vehicle that prevents the robot, but not the safety cable, from falling and makes the robot's bipedal walking steadier, connection means enabling the robot to be connected to a roller coaster (tram railway) in order to provide the effect of a flying robot, and a tunnel in which various villain robots are installed to provide an experience of the robot engaging in combat, and safety rails installed and connected in all areas where the robot moves. | 06-16-2011 |
In-Sang Song, Chungcheongnam-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090085184 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same, and more particularly, a semiconductor package and a method of fabricating the semiconductor package. The semiconductor package includes a first package that comprises a first substrate, at least one first semiconductor chip stacked on the first substrate, and first conductive pads exposed on a top surface of the first substrate; a second package disposed below the first package such that the second package comprises a second substrate, at least one second semiconductor chip, and second conductive pads exposed on a bottom surface of the second substrate; and a connection unit that extends from the first conductive pads to the second conductive pads such that the connection unit covers a side surface of the first package and a side surface of the second package in order to electrically connect the first package to the second package. | 04-02-2009 |