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| 20100086450 | METHOD AND APPARATUS FOR PREPARING CATALYST SLURRY FOR FUEL CELLS - The present invention relates to a method and apparatus for preparing a catalyst slurry for fuel cells, in which nano-sized catalyst particles are dispersed uniformly at a high concentration and the adsorption force between the catalyst and ionomer is maximized. The resulting catalyst slurry is suitable for the manufacture of a membrane-electrode assembly (MEA) of a polymer electrolyte (or proton exchange) membrane fuel cell (PEMFC). | 04-08-2010 |
| 20110053051 | ELECTRODE CATALYST COMPOSITION FOR FUEL CELL AND METHOD OF MANUFACTURING THE SAME - The present invention provides an electrode binder for a polymer electrolyte membrane fuel cell which includes a hydrocarbon-based polymer and a water-soluble polymer acting as a porogen, a porous hydrocarbon-based electrode catalyst layer including the electrode binder, and a method of manufacturing the same. Because of the use of the porogen, the pore size and porosity of the hydrocarbon-based binder catalyst layer are optimized, and bondability of a hydrocarbon-based membrane electrode assembly is enhanced. The present invention also features a fuel cell manufactured using the porogen. | 03-03-2011 |
| 20110129759 | ELECTRODE FOR POLYMER ELECTROLYTE MEMBRANE FUEL CELL AND METHOD FOR FORMING MEMBRANE-ELECTRODE ASSEMBLY USING THE SAME - The present invention provides an electrode for a polymer electrolyte membrane fuel cell (PEMFC) and a method for forming a membrane-electrode assembly (MEA) using the same, in which carbon nanofibers are added to a catalyst layer to increase the mechanical strength of the catalyst layer and to maintain the thickness of the catalyst layer after operation for a long time, thus preventing a reduction in physical durability of the fuel cell, and cerium-zirconium oxide (CeZrO | 06-02-2011 |
| 20110201756 | NOVEL AMPHIPHILIC BLOCK COPOLYMER, METHOD FOR MANUFACTURING THE SAME, AND POLYMER ELECTROLYTE MEMBRANE USING THE SAME - The present invention provides an amphiphilic block copolymer, a method for manufacturing the same, and a fuel cell membrane using the same. According to preferred embodiments, the amphiphilic block copolymer may contain poly(arylene sulfone ether ketone) (PSEK) as a hydrophobic component and poly(sulfonated styrene-co-acrylonitrile) (PSSAN) as a hydrophilic component. According to other preferred embodiments, polymer electrolyte membrane manufactured using the amphiphilic block copolymer has certain advantages in that the hydrogen ion conductivity is not reduced even at a high temperature of more than 100° C. but is rather increased and the thermal and chemical dimensional stability is excellent. | 08-18-2011 |
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| 20080242795 | Flameproof Copolymer and Flame Retardant Thermoplastic Resin Composition Including the Same - Disclosed herein is a flameproof copolymer comprising repeating units of (A) about 80 to about 99% by weight of a (meth)acrylic monomer and (B) about 1 to about 20% by weight of a vinyl-containing phosphorous monomer. The present invention also provides a thermoplastic resin composition including the flameproof copolymer. | 10-02-2008 |
| 20090012217 | Flameproof Thermoplastic Resin Composition - A flameproof thermoplastic resin composition can include (A) about 5 to about 40% by weight of an epoxy group-containing rubber modified aromatic vinyl copolymer resin, (B) about 30 to about 90% by weight of a polycarbonate resin, (C) about 1 to about 50% by weight of a polyester resin and (D) about 5 to about 30 parts by weight of a phosphorus-containing flame retardant, per 100 parts by weight of a base resin comprising (A), (B) and (C). | 01-08-2009 |
| 20090118402 | Scratch-Resistant Flameproof Thermoplastic Resin Composition - Disclosed herein is a flame retardant thermoplastic resin composition that has superior scratch resistance and mechanical properties, satisfying requirements for the appearance of housing materials resulting from a recent increase in volume of electrical and electronic products, and that contains a phosphorus-based flame-retarding agent, satisfying requirements for fire safety and prevention of environmental problems. The resin composition with scratch resistance comprises a base resin comprising (A) about 30 to about 90 parts by weight of a polycarbonate resin, (B) about 15 to about 50 parts by weight of a polymethylmethacrylate resin and (C) about 5 to about 50 parts by weight of a polyethylene terephthalate-based resin, and (D) about 5 to about 30 parts by weight of a phosphorus-based flame-retarding agent based on 100 parts by weight of the base resin. The composition may further comprise about 1 to about 30 parts by weight of an impact modifier based on 100 parts by weight of the base resin. | 05-07-2009 |
| 20090203819 | Flameproof Thermoplastic Resin Composition - Disclosed herein is a flameproof thermoplastic resin composition comprising (A) about 5 to about 40 parts by weight of a rubber modified aromatic vinyl copolymer resin; (B) about 30 to about 90 parts by weight of a polycarbonate resin; (C) about 30 to about 90 parts by weight of a polyester resin comprising (c1) about 0.01 to about 99% by weight of a semi-crystalline polyester resin and (c2) about 1 to about 99.99% by weight of a noncrystalline polyester resin; and (D) about 5 to about 30 parts by weight of an aromatic phosphate ester compound, per 100 parts by weight of a base resin comprising (A), (B) and (C). | 08-13-2009 |
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| 20090034313 | SEMICONDUCTOR MEMORY DEVICE AND LAYOUT STRUCTURE OF SUB-WORD LINE CONTROL SIGNAL GENERATOR - A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance. | 02-05-2009 |
| 20110075505 | SEMICONDUCTOR MEMORY DEVICE AND LAYOUT STRUCTURE OF SUB-WORD LINE CONTROL SIGNAL GENERATOR - A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance. | 03-31-2011 |
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| 20080307285 | MEMORY DEVICES AND SYSTEMS INCLUDING ERROR-CORRECTION CODING AND METHODS FOR ERROR-CORRECTION CODING - In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer. | 12-11-2008 |
| 20090034315 | Memory core and semiconductor memory device having the same - A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line driving signal to provide the first word-line driving signal to an array unit. The first sub word-line control signal generating circuit is disposed in the first region, and generates the first sub word-line control signal based on a sub word-line driving signal. Therefore, the memory core has a small size and, consequently so can the semiconductor device. | 02-05-2009 |
| 20090039948 | CHARGE PUMP CIRCUIT AND CHARGE PUMPING METHOD THEREOF - A charge pump circuit includes first and second charge pumps and a detector. The first charge pump outputs a first charge pump signal of an intermediate voltage level by performing a charge pumping operation in response to a command signal. The detector outputs a detection signal in response to the command signal when a voltage level of an output node is lower than a designated voltage voltage. The second charge pump charge-pumps the voltage level of the output node to a target charge-pumped voltage level higher than the intermediate voltage level and the designated voltage in response to the detection signal and the first charge pump signal. | 02-12-2009 |
| 20100237918 | Frequency measuring circuit and semiconductor device having the same - A frequency measuring circuit and a semiconductor device having the frequency measuring circuit include a divided and shifted clock signal generator, a delayed clock signal generator and a phase detecting unit. The divided and shifted clock signal generator divides a frequency of a clock signal input from an exterior to output a frequency-divided clock signal, and delays the frequency-divided clock signal by a time proportional to a period of the clock signal to output a shifted clock signal. The delayed clock signal generator delays the frequency-divided clock signal by a fixed time to generate a plurality of delayed clock signals. The phase detecting unit receives the plurality of delayed clock signals and the shifted clock signal and detects a phase difference between each of the plurality of delayed clock signals and the shifted clock signal to output a plurality of phase detecting signals that represent information related to a frequency of the clock signal | 09-23-2010 |
| 20110090728 | MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line driving signal to provide the first word-line driving signal to an array unit. The first sub word-line control signal generating circuit is disposed in the first region, and generates the first sub word-line control signal based on a sub word-line driving signal. Therefore, the memory core has a small size and, consequently so can the semiconductor device. | 04-21-2011 |
