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| 20090019449 | Load balancing method and apparatus in symmetric multi-processor system - Provided are a load balancing method and a load balancing apparatus in a symmetric multi-processor system. The load balancing method includes selecting at least two processors based on a load between a plurality of processors, from among the plurality of processors, migrating a predetermined task stored in a run queue of a first processor to a migration queue of a second processor, and migrating the predetermined task stored in the migration queue of the second processor to a run queue of the second processor. Accordingly, a run queue of a processor is not blocked while migrating a task, an immediate response of the run queue is possible, and a waiting time of a scheduler is reduced. Consequently, the scheduler can speedily perform context switching, and thus performance of the entire operating system is improved. | 01-15-2009 |
| 20090063790 | Method and apparatus for managing configuration memory of reconfigurable hardware - Provided is a method of managing a configuration memory of reconfigurable hardware which can reconfigure hardware according to hardware configuration information. The method includes: determining at least one slot capable of currently storing the hardware configuration information on the basis of the states of a plurality of slots of the configuration memory; and storing hardware configuration information, which is stored in an external memory, in the determined at least one slot capable of currently storing the hardware configuration information. Accordingly, memory utilization can be improved even in dynamic environment such as data dependent control flow or multi-tasking. | 03-05-2009 |
| 20100115169 | Processor and interrupt handling method - Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode in which the plurality of processing elements share a single task to process the single task in parallel. The processor may delay entering the parallel processing mode based on the prediction. The processor may reduce overhead that stores a context of the plurality of processing elements when the interrupt occurs. | 05-06-2010 |
| 20100115529 | Memory management apparatus and method - A memory management apparatus and a memory management method may divide an external memory area assigned to a task into a first area and a second area, and load data stored in the first area into an internal memory of a processor while the task is performed by the processor. | 05-06-2010 |
| 20110016285 | Apparatus and method for scratch pad memory management - Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory. | 01-20-2011 |
| 20110119656 | Computing system, method and computer-readable medium processing debug information in computing system - Disclosed are a system, method and computer-readable medium related to processing debug information from an embedded system. Source code of an application program to be used in an embedded system may be compiled by a computing system. The application program may include a debug code line. A minimum amount of debug information is stored in an embedded system, reducing memory overhead and waste of clock cycles of a processor. | 05-19-2011 |
| 20110252258 | HARDWARE ACCELERATION APPARATUS, METHOD AND COMPUTER-READABLE MEDIUM EFFICIENTLY PROCESSING MULTI-CORE SYNCHRONIZATION - Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Additionally, when a lock variable is returned, a wakeup signal may be transmitted to a processor core operated in the low power sleep mode, and the processor core may be activated. | 10-13-2011 |
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| 20080310227 | SEMICONDUCTOR MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier. | 12-18-2008 |
| 20090052253 | Memory device and method reducing fluctuation of read voltage generated during read while write operation - Provided is a device and method for reducing a fluctuation of a read voltage generated during a read while write (RWW) operation. A semiconductor memory device may include a write voltage generator configured to generate a write voltage to perform the write operation to at least one of a plurality of banks where the write voltage generator generates the write voltage to have a voltage level of a read voltage before the write operation changes to a read operation. The semiconductor device may also include a read voltage generator configured to generate a read voltage to perform the read operation to at least one of the other plurality of banks and/or a plurality of switches configured to switch a voltage applied to at least one of the banks to one of the write voltage and the read voltage in response to a plurality of control signals. | 02-26-2009 |
| 20090185418 | FLASH MEMORY DEVICE CONFIGURED TO SWITCH WORDLINE AND INITIALIZATION VOLTAGES - Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal. | 07-23-2009 |
| 20110019472 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A nonvolatile semiconductor memory device and a programming method thereof are provided. The programming method includes first programming a cell among a plurality of adjacent memory cells to the highest threshold voltage distribution corresponding to a data state, and subsequently programming the other adjacent cells to the lower threshold voltage distributions corresponding to second and third data states. The second data state and the third data state may have the second highest threshold voltage distribution and the third highest threshold voltage distribution, respectively, or the third highest threshold voltage distribution and the second highest threshold voltage distribution, respectively. | 01-27-2011 |
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| 20090165532 | JIG frame for drop test of flat panel display - A jig frame for a drop test of a flat panel display, which is designed to allow a tester to effectively identify if the flat panel display is damaged and to easily adjust its weight and degree of deformation is provided. The jig frame for a drop test of a flat panel display includes a base plate having a groove for receiving the flat panel display and a cover plate fixing the flat panel display by covering the flat panel display and being coupled to the base plate. The cover plate is formed of transparent material so that the flat panel display installed in the jig frame is visible to outside of the cover plate. | 07-02-2009 |
| 20090168318 | Organic light emitting diode display - An organic light emitting diode (OLED) display has an increased mechanical strength by improving the shape of a bezel combined to a panel assembly. The OLED display includes a panel assembly having a display area and a pad area, and a bezel accommodating the panel assembly. The bezel includes a bottom part on which the panel assembly is mounted, a side wall provided on a side of the bezel, and a hemming flange provided at another side of the bezel on which the side wall is not provided. The panel assembly is mounted in a manner that the pad area is turned towards the another side. | 07-02-2009 |
| 20090185339 | Flat panel display apparatus - A flat panel display apparatus includes a flat display panel including first and second substrates facing each other with a display unit therebetween, the first substrate extending beyond the second substrate, a portion of the first substrate extending beyond the second substrate defining a protruding portion, an outermost edge of the protruding portion defining a protruding edge of the first substrate, and corners of the protruding portion being chamfered, and a bezel surrounding the flat display panel. | 07-23-2009 |
| 20090195485 | Organic light emitting diode display - An OLED display that is enhanced in mechanical strength by improving a structure of a bezel supporting a panel assembly. The OLED display includes a panel assembly that includes a display region, a pad region, and a plurality of OLEDs arranged in the display region and a bezel coupled to the panel assembly, the bezel including synthetic resin, wherein, when a diagonal length of the display region is in the range of 25.4 to 101.6 mm, the bezel being designed to satisfy the following inequality t≧0.0003×a, where t(mm) is a thickness of the bezel and a(mm | 08-06-2009 |
| 20090257181 | Organic light emitting diode display and method of manufacturing the same - An organic light emitting diode display that includes a display panel and a bezel to receive the display panel, the bezel including a first bezel and a second bezel, each of the first bezel and the second bezel including different materials and including a bottom portion and a skirt portion protruding from edges of the bottom portion. | 10-15-2009 |
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| 20090066643 | TOUCH SCREEN PANEL TO INPUT MULTI-DIMENSION VALUES AND METHOD FOR CONTROLLING TOUCH SCREEN PANEL - A touch screen panel to input multi-dimension values and a method of controlling the touch screen panel are provided. In the touch screen panel, a touch screen unit displays a multi-dimensional coordinate system, and senses whether a certain point of the multi-dimensional coordinate system is touched, a control unit calculates coordinates of the touched point if the touched point is sensed, and a coordinate display unit displays values of the calculated coordinates. | 03-12-2009 |
| 20100060921 | IMAGE FORMING APPARATUS, IMAGE FORMING SYSTEM AND CONTROL METHOD IN IMAGE FORMING APPARATUS - An image forming apparatus, an image forming system including the same, and a control method of the image forming apparatus, the image forming apparatus including: an output unit; a scanning unit to scan a damaged bank note and generate image data therefrom; and a controller to calculate an area of the damaged bank note using the generated image data of the scanned damaged bank note and to control the output unit to output damaged bank note information including the calculated area of the damaged bank note and/or an exchangeable value of the damaged bank note corresponding to the area of the damaged bank note. | 03-11-2010 |
| 20110130173 | MOBILE DEVICE AND CONTROL METHOD THEREOF - The mobile device for providing a haptic function includes a vibration unit which generates vibration for a tactile effect as the haptic function; and a control unit which includes a platform providing an application programming interface (API) corresponding to the haptic function and having a plurality of parameters, executes an application prepared by the API, determines a characteristic of the vibration based on the plurality of parameters set up in the application, and controls the vibration unit to generate the vibration having the determined characteristic. | 06-02-2011 |
