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Illing

Gerhard Illing, Emden DE

Patent application numberDescriptionPublished
20100307974PREPARATION AND USE OF NOVEL POLYANILINES FOR WATER TREATMENT - The invention relates to a polyaniline, comprising aniline units and organosulphur units, characterized in that the polyaniline is doped and has a number average degree of polymerization of approximately 5 to approximately 50. The scope of the invention also includes a process for the preparation of polyaniline, wherein aniline and at least one organosulphur unit are converted to a polyaniline derivative in an oxidative, acid-catalyzed polymerization reaction. A subject of the invention is also a coated substrate which is coated with the polyaniline according to the invention and also a process for the coating of the substrate. The scope of the invention furthermore also includes a coating composition which is suitable for the coating of the substrate. The invention thus also relates to a process for the preparation of the coating composition. A subject of the invention is also the use of polyaniline which is doped and has sulphur in the main polymer chain for water treatment and/or for the purification of air and also a purification reactor for carrying out the purification process.12-09-2010

Matthias Illing, Palo Alto, CA US

Patent application numberDescriptionPublished
20090222231Method and device for correcting a signal of a sensor - A method and a device for correcting a signal of a sensor provide for maximally accurate drift compensation of a characteristics curve of the sensor. At least one characteristic quantity of the signal of the sensor is compared with a reference value. The signal of the sensor is corrected as a function of the comparison result. A value of the at least one characteristic quantity of the signal of the sensor derived from the signal of the sensor is formed as the reference value.09-03-2009
20090236610Method for Manufacturing a Semiconductor Structure, and a Corresponding Semiconductor Structure - A method for manufacturing a semiconductor structure is provided which includes the following operations: supplying a crystalline semiconductor substrate, providing a porous region adjacent to a surface of the semiconductor substrate, introducing a dopant into the porous region from the surface, and thermally recrystallizing the porous region into a crystalline doping region of the semiconductor substrate whose doping type and/or doping concentration and/or doping distribution are/is different from those or that of the semiconductor substrate. A corresponding semiconductor structure is likewise provided.09-24-2009
20100035068Method for producing a silicon substrate having modified surface properties and a silicon substrate of said type - A method for producing a silicon substrate, including the steps of providing a silicon substrate having an essentially planar silicon surface, producing a porous silicon surface having a plurality of pores, in particular having macropores and/or mesopores and/or nanopores, applying a filling material that is to be inserted into the silicon, which has a diameter that is less than a diameter of the pores, inserting the filling material into the pores and removing the excess filling material form the silicon surface, if necessary, and tempering the silicon substrate that is furnished with the filling material that has been filled into the pores, at a temperature between ca. 1000° C. and ca. 1400° C., in order to close the generated pores again and to enclose the filling material.02-11-2010
20100283147 METHOD FOR PRODUCING A PLURALITY OF CHIPS AND A CHIP PRODUCED ACCORDINGLY - A production method for chips, in which as many method steps as possible are carried out in the wafer composite, that is, in parallel for a plurality of chips disposed on a wafer. This is a method for producing a plurality of chips whose functionality is implemented on the basis of the surface layer of a substrate. In this method, the surface layer is patterned and at least one cavity is produced below the surface layer, so that the individual chip regions are connected to each other and/or to the rest of the substrate by suspension webs only, and/or so that the individual chip regions are connected to the substrate layer below the cavity via supporting elements in the region of the cavity. The suspension webs and/or supporting elements are cut when the chips are separated. The patterned and undercut surface layer of the substrate is embedded in a plastic mass before the chips are separated.11-11-2010
20110019337METHOD OF MANUFACTURING A PLANAR ELECTRODE WITH LARGE SURFACE AREA - A method for fabricating a pair of large surface area planar electrodes. The method includes forming a first template above a first substrate, the first template having a first plurality of pores, coating the first plurality of pores of the first template with a first layer of conducting material to form a first electrode, placing the first plurality of pores of the first electrode in proximity to a second electrode, thereby forming a gap between the first plurality of pores and the second electrode, and filling the gap with an electrolyte material.01-27-2011

Patent applications by Matthias Illing, Palo Alto, CA US

Matthias Illing, Kusterdingen DE

Patent application numberDescriptionPublished
20090206422Micromechanical diaphragm sensor having a double diaphragm - A method for producing a micromechanical diaphragm sensor, and a micromechanical diaphragm sensor produced with the method. The micromechanical diaphragm sensor has at least one first diaphragm as well as a second diaphragm, which is disposed essentially on top of the first diaphragm. Furthermore, the micromechanical diaphragm sensor has a first cavity and a second cavity, which is essentially disposed above the first cavity.08-20-2009
20110151620METHOD FOR MANUFACTURING CHIPS - A method for manufacturing chips (06-23-2011
20110169107Method for manufacturing a component, method for manufacturing a component system, component, and component system - A process for manufacturing a component is described. In a first manufacturing step a base structure having a substrate, a diaphragm, and a cavern region is provided. The diaphragm is oriented substantially parallel to a main plane of extension of the substrate. The cavern region is situated between the substrate and the diaphragm, and has an access opening. In a second manufacturing step, a first conductive layer is provided at least partially in the cavern region, in particular on a second side of the diaphragm facing the substrate, perpendicularly to the main plane of extension.07-14-2011

Patent applications by Matthias Illing, Kusterdingen DE

Nicola Illing, Cape Town ZA

Patent application numberDescriptionPublished
20120046183 METHOD OF DIAGNOSING A MENTAL STATE - A method of assessing a psychiatric disorder, behavioural problem or mental state following exposure to stress is described. Expression levels of mRNA transcripts for a plurality of genes linked to a stress-related neural state in the peripheral blood of a subject are measured. The expression levels of the genes, relative to a reference set of expression levels for the same genes in a healthy subject, are used to predict or assess a psychiatric disorder following exposure to a stressor.02-23-2012

Robert Illing, Villach AT

Patent application numberDescriptionPublished
20100079119SYSTEM AND METHOD FOR LIMITING CURRENT OSCILLATION - A system and method for limiting current oscillation in power supplies. A method for operating a power supply comprises entering a current limitation mode, setting a current limit for a current flowing through a power switch of the power supply, and in response to determining a current limit has changed from a high value to a low value or detecting an occurrence of a fault condition, setting the current limit to the low value, and locking the current limit so that the current limit does not change. The method further comprises providing a current to a load coupled to the power supply.04-01-2010
20100079193SEMICONDUCTOR SWITCH AND METHOD FOR OPERATING A SEMICONDUCTOR SWITCH - A semiconductor switch, is provided that comprises a semiconductor element having a control terminal and two load terminals forming switching contacts of the semiconductor switch, a temperature measuring device for measuring the temperatures of the semiconductor element at two measurement locations spaced apart from one another, and also a control circuit connected between the temperature measuring device and the control terminal of the semiconductor element and having a control input forming the control contact of the semiconductor element, wherein provision is made for: measuring the temperatures of the semiconductor element at two measurement locations spaced apart from one another; providing a signal representing the difference between the two temperatures; driving a driving current of specific intensity into the control terminal of the semiconductor element if a corresponding signal is present at the control input in order to control the semiconductor element in the conducting state between its load terminals; increasing the intensity of the driving current if the semiconductor element is controlled in the conducting state and the temperature difference exceeds a first limit value.04-01-2010
20100079197Method for Operating a Power Semiconductor Circuit and Power Semiconductor Circuit - In a method for operating a power semiconductor circuit a power semiconductor chip is provided which includes a power semiconductor switch with a first load terminal and with a second load terminal. Further, a first temperature sensor which is thermally coupled to the power semiconductor switch and a second temperature sensor are provided. The power semiconductor switch is switched OFF or kept switched OFF if the temperature difference between a first temperature of the first temperature sensor and a second temperature of the second temperature sensor is greater than or equal to a switching-OFF threshold temperature difference which depends, following an inconstant first function, on the voltage drop across the power semiconductor switch between the first load terminal and the second load terminal.04-01-2010
20110109372Semiconductor Device with Thermal Fault Detection - A semiconductor device with a thermal fault detection is disclosed. According to one example of the invention such a semiconductor device includes a semiconductor chip including an active area. It further includes a temperature sensor arrangement that provides a measurement signal dependent on the temperature in or close to the active area, the measurement signal having a slope of a time-dependent steepness, and an evaluation circuit that is configured to provide an output signal that is representative of the steepness of the slope of the measurement signal and further configured to signal a steepness higher than a predefined threshold.05-12-2011
20110157756Semiconductor Device with Overcurrent Protection - A semiconductor device with an over-current detection feature is disclosed. According to an example of the invention the device includes: a semiconductor chip including a load current path that conducts a load current in response to an input signal activating the load current flow. A current sensor arrangement provides a measurement signal representing the load current. An evaluation circuit is configured to compare the measurement signal with a first threshold and to signal an over-current when the measurement signal exceeds the first threshold after a delay time period starting from the activation of the load current flow has elapsed.06-30-2011
20110316606Power Switch Temperature Control Device and Method - An embodiment method for power switch temperature control comprises monitoring a power transistor for a delta-temperature fault, and monitoring the power transistor for an over-temperature fault. If a delta-temperature fault is detected, then the power transistor is commanded to turn off. If an over-temperature fault is detected, then the power transistor is commanded to turn off, and delta-temperature hysteresis cycling is disabled.12-29-2011