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Illikkal, OR

Ramesh Illikkal, Portland, OR US

Patent application numberDescriptionPublished
20080235457Dynamic quality of service (QoS) for a shared cache - In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.09-25-2008
20080235487Applying quality of service (QoS) to a translation lookaside buffer (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to store a priority level associated with an agent that requested storage of the data in the TLB, and an identifier field to store an identifier of the agent, where the TLB is apportioned according to a plurality of priority levels. Other embodiments are described and claimed.09-25-2008
20090006755Providing application-level information for use in cache management - In one embodiment, the present invention includes a method for associating a first identifier with data stored by a first agent in a cache line of a cache to indicate the identity of the first agent, and storing the first identifier with the data in the cache line and updating at least one of a plurality of counters associated with the first agent in a metadata storage in the cache, where the counter includes information regarding inter-agent interaction with respect to the cache line. Other embodiments are described and claimed.01-01-2009
20090165004Resource-aware application scheduling - In one embodiment, a method provides capturing resource monitoring information for a plurality of applications; accessing the resource monitoring information; and scheduling at least one of the plurality of applications on a selected processing core of a plurality of processing cores based, at least in part, on the resource monitoring information.06-25-2009
20100250998METHODS AND APPARATUSES FOR CONTROLLING THREAD CONTENTION - An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.09-30-2010

Patent applications by Ramesh Illikkal, Portland, OR US

Ramesh Kumar Illikkal, Portland, OR US

Patent application numberDescriptionPublished
20080250415Priority based throttling for power/performance Quality of Service - A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.10-09-2008

Rameshkumar G. Illikkal, Portland, OR US

Patent application numberDescriptionPublished
20080244221EXPOSING SYSTEM TOPOLOGY TO THE EXECUTION ENVIRONMENT - Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to populate a data structure with information regarding a relationship between the execution cores and the resources.10-02-2008
20100098060 METHOD AND APPARATUS FOR CONNECTING PACKET TELEPHONY CALLS BETWEEN SECURE AND NON-SECURE NETWORKS - Described herein is a method and apparatus for connecting packet telephony calls between secure networks and non-secure networks. A first telephony stream having information content for delivery to a first address may be received wherein the first telephony stream is formatted according to a first communication protocol used by a first network. The first telephony stream may be terminated at a secure boundary between the first network and a second network. A second address associated with the first address may be identified. A second telephony stream having the information content and formatted according to the second communication protocol may be delivered to the second address04-22-2010
20110087843Monitoring cache usage in a distributed shared cache - An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.04-14-2011
20110113200METHODS AND APPARATUSES FOR CONTROLLING CACHE OCCUPANCY RATES - Embodiments of an apparatus for controlling cache occupancy rates are presented. In one embodiment, an apparatus comprises a controller and monitor logic. The monitor logic determines a monitored occupancy rate associated with a first program class. The first controller regulates a first allocation probability corresponding to the first program class, based at least on the difference between a requested occupancy rate and the first monitored occupancy rate.05-12-2011

Patent applications by Rameshkumar G. Illikkal, Portland, OR US