Illikkal
Mashood Puthan Beetil Illikkal, Andover, MA US
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20150335244 | Monitor Defibrillator Telemedicine Server - A system and device ( | 11-26-2015 |
Ramesh Illikkal, Folsom, CA US
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20130191666 | Methods and Apparatuses for Controlling Thread Contention - An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold. | 07-25-2013 |
20140115259 | Methods And Apparatuses For Controlling Thread Contention - An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold. | 04-24-2014 |
20140215240 | Methods And Apparatuses For Controlling Thread Contention - An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold. | 07-31-2014 |
20150095675 | Methods And Apparatuses For Controlling Thread Contention - An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold. | 04-02-2015 |
Ramesh G. Illikkal, Folsom, CA US
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20130326101 | INTERRUPT RETURN INSTRUCTION WITH EMBEDDED INTERRUPT SERVICE FUNCTIONALITY - An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt. | 12-05-2013 |
Rameshkumar Illikkal, Folsom, CA US
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20140295886 | GEOGRAPHICAL CONTENT ADDRESSING - Methods and apparatus relating to geographic content addressing are described. In an embodiment, a server (such as a content server or a content delivery server) transmits content to one or more devices at a first location based on location information corresponding to the first location of the one or more devices. The location information corresponding to the first location of the one or more devices is registered prior to transmission of the content to the one or more devices at the first location (e.g., at a registry server). Other embodiments are also claimed and described. | 10-02-2014 |
Rameshkumar G. Illikkal, Folcom, CA US
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20130262902 | POWER EFFICIENT PROCESSOR ARCHITECTURE - In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed. | 10-03-2013 |
Rameshkumar G. Illikkal, Folsom, CA US
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20140314323 | OPTIMIZED FAST HESSIAN MATRIX COMPUTATION ARCHITECTURE - Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation. | 10-23-2014 |