Patent application number | Description | Published |
20090065810 | III-NITRIDE BIDIRECTIONAL SWITCHES - Bidirectional switches are described. The bidirectional switches include first and a second III-N based high electron mobility transistor. In some embodiments, the source of the first transistor is in electrical contact with a source of the second transistor. In some embodiments, the drain of the first transistor is in electrical contact with a drain of the second transistor. In some embodiments, the two transistors share a drift region and the switch is free of a drain contact between the two transistors. Matrix converters can be formed from the bidirectional switches. | 03-12-2009 |
20090072240 | III-Nitride Devices with Recessed Gates - III-nitride devices are described with recessed gates. In some embodiments, the material around the gates is formed by epitaxially depositing different III-nitride layers on a substrate and etching through at least the top two layers in the gate region. Because adjacent layers in the top three layers of the structure have different compositions, some of the layers act as etch stops to allow for precision etching. In some embodiments, a regrowth mask is used to prevent growth of material in the gate region. A gate electrode is deposited in the recess. | 03-19-2009 |
20090146185 | INSULATED GATE E-MODE TRANSISTORS - Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the gate region, that is, in the access region. | 06-11-2009 |
20090267078 | Enhancement Mode III-N HEMTs - A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate. | 10-29-2009 |
20100140660 | Semiconductor Heterostructure Diodes - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 06-10-2010 |
20110127541 | SEMICONDUCTOR HETEROSTRUCTURE DIODES - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 06-02-2011 |
20120267640 | SEMICONDUCTOR HETEROSTRUCTURE DIODES - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 10-25-2012 |
20120319127 | CURRENT APERTURE VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P-TYPE GALLIUM NITRIDE AS A CURRENT BLOCKING LAYER - A current aperture vertical electron transistor (CAVET) with ammonia (NH | 12-20-2012 |
20130316502 | Enhancement Mode III-N HEMTs - A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate. | 11-28-2013 |
20140001557 | SEMICONDUCTOR DEVICES WITH INTEGRATED HOLE COLLECTORS | 01-02-2014 |
20140054603 | Semiconductor Heterostructure Diodes - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 02-27-2014 |
20140070959 | SYSTEM FOR MONITOR AND CONTROL OF EQUIPMENT - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining a current location and receiving energy usage information from devices in the location. | 03-13-2014 |
20140361309 | Enhancement Mode III-N HEMTs - A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate. | 12-11-2014 |