| Patent application number | Description | Published |
|---|
| 20080211084 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER - An integrated circuit package system includes: providing a mountable integrated circuit system having an encapsulation with a cavity therein and a first interposer exposed by the cavity; mounting a second interposer over the first interposer for only stacking a discrete device thereover, and with the second interposer over the encapsulation and the cavity; and mounting an electrical component over the second interposer. | 09-04-2008 |
| 20080237873 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BONDING IN VIA - An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening in the substrate open at the top and having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor. | 10-02-2008 |
| 20080258289 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING - An integrated circuit package system comprising: forming an area array substrate; mounting surface conductors on the area array substrate; forming a molded package body on the area array substrate and the surface conductors; providing a step in the molded package body; and exposing a surface conductor by the step. | 10-23-2008 |
| 20080272487 | SYSTEM FOR IMPLEMENTING HARD-METAL WIRE BONDS - A wire bond system including providing an integrated circuit die with a bond pad thereon, forming a soft bump on the bond pad, and wire bonding a hard-metal wire on the soft bump. | 11-06-2008 |
| 20080283998 | ELECTRONIC SYSTEM WITH EXPANSION FEATURE - An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad. | 11-20-2008 |
| 20080290485 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RELIEF - An integrated circuit package system including: providing a die pad with a top, sides, and a bottom, the bottom having a relief with a flat surface and defining a wall and a center pad; mounting a barrier under the bottom of the die pad; mounting an integrated circuit die on the top of the die pad; encapsulating the integrated circuit die and the top and sides of the die pad with the wall preventing encapsulation from flowing along the barrier to reach the center pad; and mounting an external interconnect on the center pad. | 11-27-2008 |
| 20080296759 | SEMICONDUCTOR PACKAGES - A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via. | 12-04-2008 |
| 20090014866 | MULTICHIP MODULE PACKAGE AND FABRICATION METHOD - A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink. | 01-15-2009 |
| 20090016032 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEXIBLE SUBSTRATE AND RECESSED PACKAGE - An integrated circuit package system includes: providing a flexible circuit substrate having a fold; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulating the integrated circuit or integrated circuit package with a recessed encapsulation having a first level and a second level, the second level having the flexible circuit substrate folded thereover. | 01-15-2009 |
| 20090016033 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEXIBLE SUBSTRATE AND MOUNDED PACKAGE - An integrated circuit package system includes: providing a flexible circuit substrate; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulating the integrated circuit or integrated circuit package with a mounded encapsulation having a first level and a second level, the second level having the flexible circuit substrate folded thereover. | 01-15-2009 |
| 20090032932 | INTEGRATED CIRCUIT PACKAGING SYSTEM FOR FINE PITCH SUBSTRATES - An integrated circuit packaging system comprising: forming a substrate including; patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof. | 02-05-2009 |
| 20090079049 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP - An integrated circuit package system includes: providing an integrated circuit wafer having an active side and a backside; forming a stress-relieving layer on the backside; forming an adhesion layer on the stress-relieving layer; dicing the integrated circuit wafer into a semiconductor chip with the stress-relieving layer and the adhesion layer on the backside of the semiconductor chip; and mounting the semiconductor chip over electrical interconnects. | 03-26-2009 |
| 20090146315 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM AND METHOD OF MANUFACTURE THEREOF - An integrated circuit package-on-package stacking system includes: providing a first integrated circuit package, mounting a metalized interposer substrate over the first integrated circuit package, attaching a stiffener integrated with the metalized interposer substrate and having dimensions within package extents, and attaching a second integrated circuit package on the metalized interposer substrate adjacent the stiffener. | 06-11-2009 |
| 20090152715 | Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-applied Protective Layer - A semiconductor device is made by first forming a protective layer over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer. | 06-18-2009 |
| 20090170241 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier - A semiconductor device is made by forming contact pads on a sacrificial carrier. The contact pads may be formed on a pillar. A semiconductor die is mounted to electrically connect to the contact pads with solder bumps or wire bonds. The semiconductor die is encapsulated with molding compound. The sacrificial carrier is removed. A backside interconnect structure has a first conductive layer formed over the molding compound to electrically connect to the contact pads. A first insulating layer is formed over the first conductive layer. A portion of the first insulating layer is removed to expose the first conductive layer. Solder material is deposited in electrical contact with the first conductive layer. The solder material is reflowed to form a solder bump. A wire bond electrically connects to a contact pad. A front-side interconnect structure can be formed through the molding compound to the contact pads. | 07-02-2009 |
| 20090230529 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ETCHED RING AND DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring. | 09-17-2009 |
| 20090236686 | Semiconductor Device and Method of Forming UBM Fixed Relative to Interconnect Structure for Alignment of Semiconductor Die - A semiconductor device is made by forming a first conductive layer over a temporary carrier. A UBM layer is formed over the temporary carrier and fixed in position relative to the first conductive layer. A conductive pillar is formed over the first conductive layer. A semiconductor die is mounted to the UBM layer to align the die relative to the conductive pillar. An encapsulant is deposited over the die and around the conductive pillar. The UBM layer prevents shifting of the semiconductor die while depositing the encapsulant. The temporary carrier is removed. A first interconnect structure is formed over a first surface of the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected through the conductive pillar. The first or second interconnect structure includes an integrated passive device electrically connected to the conductive pillar. | 09-24-2009 |
| 20090250798 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECT SUPPORT - An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support. | 10-08-2009 |
| 20090273062 | SEMICONDUCTOR PACKAGE HEAT SPREADER - A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate. | 11-05-2009 |
| 20090309207 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE AND PACKAGE COMBINATION - An integrated package system with die and package combination includes forming a leadframe having internal leads and external leads, encapsulating a first integrated circuit on the leadframe, and encapsulating a second integrated circuit over the first integrated circuit. | 12-17-2009 |
| 20090309212 | Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure - A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar. | 12-17-2009 |
| 20090309237 | SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HAVING DIFFERENT BONDABLE HEIGHTS AT LEAD FINGER TIPS - A semiconductor package system is provided. A substrate having a die attach paddle is provided. A first plurality of leads is provided around the die attach paddle having a first plurality of lead tips. A second plurality of leads is provided around the die attach paddle interleaved with the first plurality of leads, at least some of the second plurality of leads having a plurality of depression lead tips. A first die is attached to the die attach paddle. The die is wire bonded to the first plurality of leads and the second plurality of leads. The die is encapsulated. | 12-17-2009 |
| 20090315170 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CIRCUITRY AND POST, AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a shaped platform with a conductive post; mounting the shaped platform with the conductive post over a temporary carrier; mounting an integrated circuit device over the temporary carrier; encapsulating the conductive post and the integrated circuit device; removing a portion of the shaped platform isolating the conductive post; and removing the temporary carrier. | 12-24-2009 |
| 20090321913 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LOCKING TERMINAL - An integrated circuit package system includes: forming a first locking terminal having a first terminal recess with a top portion of the first terminal recess narrower than a bottom portion of the first terminal recess; connecting an integrated circuit and the first locking terminal; and forming a package encapsulation over the integrated circuit and in the first locking terminal. | 12-31-2009 |
| 20100001384 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD-FRAME PADDLE SCHEME FOR SINGLE AXIS PARTIAL SAW ISOLATION - An integrated circuit package system includes: providing a die-pad with a predefined slot and an integrated circuit attached to the die-pad; connecting the integrated circuit to the die-pad with a bond wire; encapsulating the integrated circuit and the bond wire with an encapsulation; and partitioning the die-pad with partial saw isolation grooves along a single axis, and into a side pad, and a die attach pad. | 01-07-2010 |
| 20100006994 | Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier - An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a lead frame interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the lead frame interconnect structure and encapsulant. The package interconnect structure and lead frame interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the lead frame interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the lead frame interconnect structure. | 01-14-2010 |
| 20100038768 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND MANUFACTURING METHOD THEREOF - A stackable multi-chip package system is provided including forming an external interconnect having a base and a tip, connecting a first integrated circuit die and the base, stacking a second integrated circuit die over the first integrated circuit die in an active side to active side configuration, connecting the second integrated circuit die and the base, and molding the first integrated circuit die, the second integrated circuit die, and the external interconnect partially exposed. | 02-18-2010 |
| 20100038771 | INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE - A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer. | 02-18-2010 |
| 20100052135 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier - A semiconductor device is made by forming a photoresist layer over a metal carrier. A plurality of openings is formed in the photoresist layer extending to the metal carrier. A conductive material is selectively plated in the openings of the photoresist layer using the metal carrier as an electroplating current path to form wettable contact pads. A semiconductor die has bumps formed on its surface. The bumps are directly mounted to the wettable contact pads to align the die with respect to the wettable contact pads. An encapsulant is deposited over the die. The metal carrier is removed. An interconnect structure is formed over the encapsulant and electrically connected to the wettable contact pads. A plurality of conductive vias is formed through the encapsulant and extends to the contact pads. The conductive vias are aligned by the wettable contact pads with respect to the die to reduce interconnect pitch. | 03-04-2010 |
| 20100133704 | Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias - A semiconductor device is fabricated by providing a carrier for supporting the semiconductor device. A first semiconductor die is mounted to the carrier. The first semiconductor die has a contact pad. A first dummy die is mounted to the carrier. The first dummy die has a through-silicon via (TSV). The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. A first interconnect structure is formed over the first semiconductor die and the first dummy die. The first interconnect structure is connected to the contact pad of the first semiconductor die and the TSV of the first dummy die. The carrier is removed and a second interconnect structure is formed over the first semiconductor die and the first dummy die. The second interconnect structure is connected to the TSV of the first dummy die. A semiconductor package is connected to the second interconnect structure. | 06-03-2010 |
| 20100140771 | Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant - A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts. | 06-10-2010 |
| 20100144101 | Semiconductor Device and Method of Forming Conductive Posts Embedded in Photosensitive Encapsulant - A semiconductor package includes a post carrier having a base plate and plurality of conductive posts. A photosensitive encapsulant is deposited over the base plate of the post carrier and around the conductive posts. The photosensitive encapsulant is etched to expose a portion of the base plate of the post carrier. A semiconductor die is mounted to the base plate of the post carrier within the etched portions of the photosensitive encapsulant. A second encapsulant is deposited over the semiconductor die. A first circuit build-up layer is formed over the second encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. The base plate of the post carrier is removed and a second circuit build-up layer is formed over the semiconductor die and the photosensitive encapsulant opposite the first circuit build-up layer. The second circuit build-up layer is electrically connected to the conductive posts. | 06-10-2010 |
| 20100155926 | INTEGRATED CIRCUIT PACKAGING SYSTEM FOR FINE PITCH SUBSTRATES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a substrate including: patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof. | 06-24-2010 |
| 20100224974 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PATTERNED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer. | 09-09-2010 |
| 20100224978 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLEX TAPE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a device to the substrate; providing interconnects on the substrate; and forming a flexible tape substantially conformal to the device and contacting the interconnects. | 09-09-2010 |
| 20100258937 | Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer - A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer. | 10-14-2010 |
| 20100289134 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH REINFORCED ENCAPSULANT HAVING EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling stacking interconnects on the component side; and forming an integrated circuit receptacle, for receiving an integrated circuit device, by molding a reinforced encapsulant on the component side and exposing a portion of the stacking interconnects. | 11-18-2010 |
| 20100289142 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an interconnect to the substrate; encapsulating the interconnect with an encapsulation leaving a portion of the interconnect not encapsulated; attaching a joint to the interconnect and simultaneously creating a coined-surface of the interconnect contacting the joint; and attaching an integrated circuit to the substrate. | 11-18-2010 |
| 20110018084 | ENCAPSULANT CAVITY INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF FABRICATION THEREOF - A method for fabricating an encapsulant cavity integrated circuit package system includes: forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity. | 01-27-2011 |
| 20110024916 | Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias - A semiconductor device has a carrier for supporting the semiconductor device. A first semiconductor die is mounted over the carrier. A first dummy die having a first through-silicon via (TSV) is mounted over the carrier. The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. The carrier is removed. A first redistribution layer (RDL) is formed over a first surface of the first semiconductor die and a first surface of the first dummy die to electrically connect the first TSV and a contact pad of the first semiconductor die. An insulation layer is formed over the first RDL. A second RDL is formed over a second surface of the first dummy die opposite the first surface of the first dummy die and electrically connected to the first TSV. A semiconductor package is connected to the second RDL. | 02-03-2011 |
| 20110037154 | Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier - An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure. | 02-17-2011 |
| 20110121449 | Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP - A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer. | 05-26-2011 |
| 20110121466 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP - An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer. | 05-26-2011 |
| 20110127678 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CIRCUITRY AND POST - An integrated circuit packaging system includes: an integrated circuit device; a conductive post adjacent the integrated circuit device, the conductive post with a contact surface having characteristics of a shaped platform removed; and an encapsulant around the conductive post and the integrated circuit device with the conductive post extending through the encapsulant and each end of the conductive post exposed from the encapsulant. | 06-02-2011 |
| 20110147926 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier - A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch. | 06-23-2011 |
