| Patent application number | Description | Published |
|---|
| 20090077349 | METHOD OF MANAGING INSTRUCTION CACHE AND PROCESSOR USING THE METHOD - A method of managing an instruction cache and a process of using the method are provided. The processor includes a processor core which has an active mode and an inactive mode, and an instruction cache which pre-traces a first instruction and detects a cache miss during the inactive mode, wherein the first instruction is performed by the processor core during the active mode. | 03-19-2009 |
| 20090077357 | Method of Power Simulation and Power Simulator - Disclosed are a method of simulating power and a power simulator. The power simulator includes a static information extracting unit that extracts static information with respect to execution of the second instruction; a dynamic information extracting unit that extracts dynamic information with respect to the execution of the second instruction; and a calculation unit that calculates an estimated power of the processor based on the static information and the dynamic information. | 03-19-2009 |
| 20090119456 | PROCESSOR AND MEMORY CONTROL METHOD - A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports. | 05-07-2009 |
| 20100174885 | RECONFIGURABLE PROCESSOR AND OPERATING METHOD OF THE SAME - Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration memory including configuration information about routing. The distributed operation configuration memory may be activated according to a predicate signal. | 07-08-2010 |
| 20100199076 | COMPUTING APPARATUS AND METHOD OF HANDLING INTERRUPT - A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the host processor processes the interrupt, and the interrupt supervisor may perform mode switching between the coarse-grained array and the host processor. | 08-05-2010 |
| 20100211760 | APPARATUS AND METHOD FOR PROVIDING INSTRUCTION FOR HETEROGENEOUS PROCESSOR - Provided are an apparatus and method for providing instructions for a heterogeneous processor having heterogeneous components supporting different data widths. Respective data widths of operands and connections in a data flow graph are determined by using type information of operands. Instructions, to be executed by the heterogeneous processor, are provided based on the determined data widths. | 08-19-2010 |
| 20100223449 | INTERRUPT HANDLING APPARATUS AND METHOD FOR EQUAL-MODEL PROCESSOR AND PROCESSOR INCLUDING THE INTERRUPT HANDLING APPARATUS - An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency. | 09-02-2010 |
| 20100274939 | RECONFIGURABLE PROCESSOR AND INTERRUPT HANDLING METHOD - An interrupt handling technology and a reconfigurable processor are provided. The reconfigurable processor includes a plurality of processing elements, and some of the processing elements are designated for interrupt handling. When an interrupt request occurs while the reconfigurable processor is executing a loop operation, the designated processing elements may process the interrupt request. The interrupt handling technology allows the interrupt request and the loop operation to be processed in parallel. | 10-28-2010 |
| 20110087821 | APPARATUS TO ACCESS MULTI-BANK MEMORY - A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made. | 04-14-2011 |
