Patent application number | Description | Published |
20130188426 | NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, PROGRAM METHOD THEREOF, AND OPERATION METHOD OF CONTROLLER CONTROLLING THE SAME - According to example embodiments, a nonvolatile memory device includes a first memory cell configured to store a first data pattern, a second memory cell configured to be programmed using a program voltage, and a coupling program control unit. The coupling program control unit may be configured to perform a verification operation for verifying whether the first memory cell is programmed with the first data pattern. The verification operation may provide to the first memory cell a verification voltage corresponding to the first data pattern. The coupling program control unit may be configured to end programming the second memory cell when the verification operation on the first memory cell indicates a pass. | 07-25-2013 |
20130223143 | NONVOLATILE MEMORY DEVICE HAVING ADJUSTABLE PROGRAM PULSE WIDTH - A method of programming a nonvolatile memory device comprises determining a temperature condition of the nonvolatile memory device, determining a program pulse period according to the temperature condition, supplying a program voltage to a selected word line using the program pulse period, and supplying a pass voltage to unselected word lines while supplying the program voltage to the selected word line. | 08-29-2013 |
20130223156 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A program method is provided for a nonvolatile memory device, including a substrate and multiple memory cells formed in a pocket well in the substrate. The program method includes supplying a program voltage to a selected word line during a program execution period of a program loop, supplying a verification voltage to the selected word line during a verification period of the program loop, and supplying a negative voltage to the pocket well as a well bias voltage during the verification period. | 08-29-2013 |
20130229217 | DYNAMIC LATCH AND DATA OUTPUT DEVICE COMPRISING SAME - A dynamic latch comprises a floating node, a storage node, a write transistor connected to the floating node and the storage node and configured to write data of the floating node to the storage node, and a read transistor connected to the floating node and configured to read the data of the storage node. | 09-05-2013 |
20130250678 | PAGE BUFFER, MEMORY DEVICE COMPRISING PAGE BUFFER, AND RELATED METHOD OF OPERATION - A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node. | 09-26-2013 |
20140056069 | NONVOLATILE MEMORY DEVICE HAVING NEAR/FAR MEMORY CELL GROUPINGS AND DATA PROCESSING METHOD - A nonvolatile memory device includes; a memory cell array designating a first memory cell group including first memory cells connected with a word line and disposed less than a reference distance from a word line voltage source in a word line direction, and a second memory cell group including second memory cells connected to the word line and disposed more than the reference distance from the word line voltage source in the word line direction, and control logic configured during a data processing operation to provide a first word line voltage to a first target memory cell among the first memory cells, and a second word line voltage different from the first word line voltage to a second target memory cell among the second memory cells. | 02-27-2014 |
20140119122 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device and a method of programming the nonvolatile semiconductor memory device are disclosed. The programming method includes applying a first voltage greater than a ground voltage to a selected word line at a first time; applying a second voltage greater than the first voltage to the selected word line at a second time that occurs after a predetermined period from the first time; applying the ground voltage to a first unselected word line directly adjacent to the selected word line at the first time; and applying a third voltage greater than the ground voltage to the first unselected word line at the second time. | 05-01-2014 |
20140119139 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a memory cell array and control logic. The memory cell array includes multiple memory blocks, each memory block including memory cells connected to word lines and bit lines. The control logic is configured to perform an erase operation in which an erase voltage is applied to a memory block of the multiple memory blocks to erase the memory cells of the memory block, and in which an erase verification voltage is applied a selected word line of the memory block to verify respective erase states of memory cells connected to the selected word line. The control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells, and to control a level of the erase verification voltage based on the erase state information. | 05-01-2014 |
20140140130 | SEMICONDUCTOR MEMORY DEVICE FOR AND METHOD OF APPLYING TEMPERATURE-COMPENSATED WORD LINE VOLTAGE DURING READ OPERATION - A semiconductor memory device configured to apply a temperature-compensated word line voltage to a word line during a data read operation includes a memory cell array including a plurality of word lines, a plurality of non-volatile memory cells connected to the word lines, and a word line voltage application unit configured to apply a temperature-compensated read voltage to a selected word line and to apply a temperature-compensated pass voltage to at least one unselected word line during a read operation. | 05-22-2014 |