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Ikenaga, Tokyo
Chikao Ikenaga, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100276806 | Plastic package and method of fabricating the same - A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals. | 11-04-2010 |
Hideo Ikenaga, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100229606 | STEREOSCOPIC KNITWORK - A three-dimensional knit fabric comprising two knit layers consisting of a front layer and a back layer and monofilament yarns connecting the two knit layers, characterized in that the three-dimensional knit fabric has a thickness of 5 to 25 mm, the fabric undergoes a compression load of 100 to 250 N for compressive deformation of 2.6 mm on a 100-mm diameter compression plate, and the front and back knit layers undergo a shearing stress of 15 to 35 N to be shifted by 5 mm in parallel to each other in transverse opposite directions (directions along the course line). | 09-16-2010 |
Kazuo Ikenaga, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100242270 | Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module - A manufacturing method for a wiring circuit board includes the steps of: forming a board on a surface of a metal layer directly or indirectly through an etching barrier layer; forming an insulating film on the surface of the metal layer; polishing the insulating film to an extent to which a top face of the bump is exposed; and forming a solder ball on the top face of the bump. | 09-30-2010 |
Kazuyuki Ikenaga, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100050349 | Cleaning apparatus and cleaning method - The invention provides a cleaning apparatus for removing particles attached to the fine roughness on the surface of an insulating body coated on the metal surface of a vacuum processing apparatus. The present cleaning apparatus comprises an adhesive sheet | 03-04-2010 |
| 20100294315 | Cleaning Method - A cleaning method using a cleaning apparatus having an adhesive sheet, a conductive sheet in contact with a base material of the adhesive sheet, and a pressing member for pressing the conductive sheet onto the adhesive sheet. The pressing member includes a voltage applier, and a pressing force controller which presses the adhesive sheet onto a curved surface of a portion to be cleaned of a vacuum processing apparatus from above the conductive sheet. The method includes pressing the pressing member by a pressing force controlled via the pressing force controller to press the conductive sheet and the adhesive sheet to adhere an adhesive surface of the adhesive sheet to the curved surface of the portion to be cleaned, and applying a voltage to the conductive sheet or applying a voltage having a temporally changed polarity. | 11-25-2010 |
Masanori Ikenaga, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20080272523 | Manufacturing apparatus and manufacturing method for tubular resin film - A manufacturing apparatus and manufacturing method are provided for manufacturing stably from a thermoplastic resin a resin film product having a small and uniform thickness and smooth surfaces, which has been impossible with a conventional tube extruding method or and blown film extrusion method. It comprises a heating extruder ( | 11-06-2008 |
Naofumi Ikenaga, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090201666 | BACKLIGHT MODULE, BACKLIGHT MODULE MANUFACTURING METHOD, LIGHTING DEVICE, DISPLAY DEVICE AND TELEVISION RECEIVER - In a backlight module, when relay connectors exposed to a back side of a chassis are engaged with the connector portions of a lighting jig, the power from the power supply source of the lighting jig is supplied to discharge tubes via the connector portions and the relay connectors. Thereby, the discharge tubes can be lighted, even if a power board is not connected to the relay connectors. At the time, the lighting jig is arranged to face the back surface of the chassis, and therefore optical sheets can be mounted to the chassis from the front side. | 08-13-2009 |
| 20090209126 | RELAY CONNECTOR, MOUNTING STRUCTURE OF RELAY CONNECTOR AND CHASSIS, AND MOUNTING STRUCTURE OF RELAY CONNECTOR AND DISCHARGE TUBE - Relay connectors are arranged to supply power from power boards arranged on the back side of a chassis having a substantially plate-shaped configuration to discharge tubes arranged on the front side of the chassis. Each relay connector includes a holder having an insulation property and to be mounted to the chassis, and further includes a relay terminal mounted to the holder and capable of electrical connection to the discharge tube and the power board. The relay terminal is immune to direct contact with the chassis. This enables the use of a metallic chassis. | 08-20-2009 |
Shinichi Ikenaga, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20080205111 | Semiconductor memory device and defect remedying method thereof - A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays. | 08-28-2008 |
Yoshifumi Ikenaga, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090201063 | DYNAMIC SEMICONDUCTOR DEVICE - A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step sections, which are alternately connected with master step sections and provided with dynamic gate sections or with latch sections and dynamic gate sections; and a timing signal generating section for generating a signal for controlling operation of the master step sections and the slave step sections. The timing signal generating section supplies the latch sections with signals for storing data of the previous step before the data is erased. | 08-13-2009 |
| 20100033235 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A control circuit controls a power-source-voltage feed circuit, and controls a power source voltage fed to a target circuit. A reference-speed monitor monitors whether or not a delay time of a critical path in the target circuit is satisfies a required operational speed. A voltage-difference monitor monitors a difference between the power source voltage of the target circuit and a threshold voltage of the target circuit, to output the voltage difference information. The control circuit determines whether to increase or decrease the power source voltage based on a result of monitoring by the reference-speed monitor. The control circuit determines the change rate of the power source voltage so that the control rate of the power source voltage is proportional to the voltage difference information output from the voltage-difference monitor. | 02-11-2010 |
| 20100327961 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND POWER SUPPLY VOLTAGE CONTROL SYSTEM - A semiconductor integrated circuit device includes: a target circuit whose at least power supply voltage is variable; a power supply voltage providing circuit feeding the target circuit with a power supply voltage; and a minimum energy point monitor circuit detecting an energy-minimizing power supply voltage which minimizes a change in the energy consumed by the target circuit upon a change in the power supply voltage. The power supply voltage delivered by the power supply voltage providing circuit is controlled so as to be equal to the energy-minimizing power supply voltage detected by the minimum energy point monitor circuit. | 12-30-2010 |
Yoshihiko Ikenaga, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090240832 | RECEIVING APPARATUS, TRANSMITTING APPARATUS, COMMUNICATION SYSTEM, AND METHOD OF DETECTING BUFFER SETTING OF RELAY SERVER - A receiving apparatus of the present invention includes: a relayed dummy data receiving unit for receiving relayed dummy data including dummy data of n bytes (n≧1) and/or dummy data of N bytes (N≧n) sequentially and repetitively transmitted from a transmitting apparatus to a relay server from the relay server; and a buffer setting detecting unit for detecting a buffer setting of the relay server based on a first size value indicative of data size of relayed dummy data received for the first time by the relayed dummy data receiving unit and a second size value indicative of not larger data size of relayed dummy data received for the second time and relayed dummy data received for the third time. | 09-24-2009 |
| 20110076854 | METHOD OF MANUFACTURING VERTICAL-CAVITY SURFACE EMITTING LASER - According to a method of manufacturing a vertical-cavity surface-emitting semiconductor laser element in accordance with the present invention, a process of wet etching is performed for a part that is oxidized in a layer of an AlGaAs ( | 03-31-2011 |