Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Ikenaga, JP
Atsushi Ikenaga, Koga-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100000556 | GLOWING ARTIFICIAL NAIL - The currently available artificial nails swell as a whole and undergo deformation, which damages the commercial value thereof. Moreover, they suffer from another problem of not evenly glowing as a whole due to the occurrence of some non-glowing spaces. In an airtight hollow container having a roughly crescent-shaped cross section and having light-permeability and flexibility, therefore, a space free from capillary action is ensured at the inside of an area joining the lower wall and the upper wall. Then, one of two kinds of compositions, which show chemical luminescence when mixed together, is packed in a breakable glass ampule in the airtight hollow container while the other composition is packed outside the glass ampule in the airtight hollow container. | 01-07-2010 |
Chikao Ikenaga, Kitamoto-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090174053 | Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device - A substrate | 07-09-2009 |
| 20110014752 | SUBSTRATE FOR SEMICONDUCTOR DEVICE, RESIN-SEALED SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAID SUBSTRATE FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAID RESIN-SEALED SEMICONDUCTOR DEVICE - A substrate for a semiconductor device includes: a base plate, a plurality of external terminal portions respectively arranged in a plane on the base plate and having external terminal faces respectively facing the base plate; a plurality of internal terminal portions, respectively arranged in the plane on the base plate and having internal terminal faces respectively facing an opposite side to the base plate. The internal terminal portions are connected with the external terminal portions via wiring portions, respectively. A part of the external terminal portions are located on the base plate in a predetermined arrangement area in which a semiconductor element is arranged. | 01-20-2011 |
Chikao Ikenaga, Shinjuku-Ku JP
| Patent application number | Description | Published |
|---|---|---|
| 20080251902 | Plastic package and method of fabricating the same - A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals. | 10-16-2008 |
Chikao Ikenaga, Saitama-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20090140411 | RESIN-SEALED SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, BASE MATERIAL FOR THE SEMICONDUCTOR DEVICE, AND LAYERED AND RESIN-SEALED SEMICONDUCTOR DEVICE - The present invention provides a resin-sealed semiconductor device, which includes a semiconductor element; a plurality of terminal members, each surrounding the semiconductor element and including an external terminal portion, an internal terminal portion and a connecting portion; bonding wires, each connecting the semiconductor element with the internal terminal portion; and a resin-sealing portion sealing the semiconductor element, terminal members and bonding wires. Each terminal member is composed of an inner thinned portion forming the internal terminal portion and an outer thickened portion forming the external terminal portion. A rear face of each internal terminal portion, and a front face, a rear face and an outer side face of each external terminal portion are exposed to the outside from the resin-sealing portion, respectively. | 06-04-2009 |
Eri Ikenaga, Yokohama JP
| Patent application number | Description | Published |
|---|---|---|
| 20090307301 | METHOD AND APPARATUS FOR CONDUCTING A TRANSACTION BETWEEN TRANSACTION PROCESSING SYSTEMS - When investigating a failure occurring in a transaction between information processing apparatuses, it is possible to reduce the time required for the failure investigation. A first local ID for identifying a transaction processing of first information processing apparatus is related with a standard ID for relating transaction processing of the first and the second information processing apparatuses with each other the related IDs and are stored in a first mapping table. The standard ID and a transaction processing request are transmitted to the second information processing apparatus to request execution of a transaction processing therefor. If a failure occurs in the requested transaction processing, a standard ID of the transaction processing concerned is specified to inquire a second local ID for identifying the transaction processing. Mapping information for relating the first local ID corresponding to the specified standard ID with the transmitted second local ID is generated. | 12-10-2009 |
Hiroaki Ikenaga, Nagoya-City JP
| Patent application number | Description | Published |
|---|---|---|
| 20110215653 | Energization control apparatus - An energization control apparatus includes a control portion, a disconnection detecting portion, and a prohibiting portion. The control portion controls energization to a plurality of loads coupled in parallel. The disconnection detecting portion repeatedly or continuously determines whether a supply current to the plurality of loads is less than a threshold value when the control portion energizes the plurality of loads, and the disconnection detecting portion detects a disconnection of a part of the plurality of loads when the supply current is less than the threshold value. The prohibiting portion prohibits a disconnection detection by the disconnection detecting portion for a predetermined period since the control portion starts to energize the plurality of loads, and the prohibiting portion enables the disconnection detection by the disconnection detecting portion after the predetermined period elapses. | 09-08-2011 |
Hirokazu Ikenaga, Ichihara-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100063341 | METHOD FOR CONVERTING HYDROCARBONS WITH ZEOLITE SHAPED CATALYST - The invention provides methods for converting hydrocarbons as starting material by industrial fixed-bed reaction processes with a zeolite shaped catalyst which has a low content of inorganic binder and a high pore volume and which shows high catalytic activity, long catalyst life and high crushing strength. A zeolite shaped catalyst used in the methods of the invention includes zeolite and an inorganic binder and is obtained by kneading zeolite, a starting material of an inorganic binder, shaping auxiliary(ies), organic polymer particles having an average diameter of 0.1 to 6 μm and water into a kneaded product, and extruding, drying and calcining the kneaded product; and the zeolite shaped catalyst has a zeolite component content of not less than 60 wt % relative to the total weight, a pore volume of 0.4 to 1.0 ml/g, a half-volume pore diameter of 80 to 500 nm and a crushing strength of not less than 0.9 kg. | 03-11-2010 |
| 20100191030 | METHOD FOR REACTIVATING METATHESIS CATALYSTS, AND OLEFIN PRODUCTION PROCESS INCLUDING REACTIVATING STEP - A metathesis catalyst which is a combination including a catalyst | 07-29-2010 |
Hirokazu Ikenaga, Chiba JP
| Patent application number | Description | Published |
|---|---|---|
| 20100063339 | PROCESS FOR PRODUCING OLEFINS - In a process for producing olefins by a metathesis reaction comprising feeding an olefin gas to pass the olefin through a catalyst bed in the presence of hydrogen gas to convert the olefin into another kind of olefin, the catalyst bed having a catalyst including at least one metal selected from the group consisting of tungsten, molybdenum, rhenium, niobium, tantalum and vanadium, and a co-catalyst including a basic compound having at least one metal selected from the group consisting of Group Ia (alkali metals), Group IIa (alkaline earth metals), Group IIb and Group IIIa of the periodic table, the improvement lies in controlling the superficial velocity of the gas passing through the catalyst bed to 0.01 to 2.0 m/sec. According to the present invention, the presence of hydrogen gas dramatically increases the durability of the metathesis catalytic activity and the by-production of paraffins is suppressed. | 03-11-2010 |
| 20110152595 | OLEFIN PRODUCTION PROCESS - A process is provided which is capable of producing olefins stably and efficiently by a metathesis reaction of identical or different olefins while preventing the lowering in metathesis catalyst activity due to trace impurities such as heteroatom-containing compounds that are contained in a starting olefin. | 06-23-2011 |
Hiroko Ikenaga, Ibaraki-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110126983 | PAINT FILM-PROTECTING SHEET - A paint film-protecting sheet ( | 06-02-2011 |
| 20110129655 | PAINT FILM-PROTECTING SHEET - A paint film-protecting sheet ( | 06-02-2011 |
Kazutoshi Ikenaga, Kumamoto JP
| Patent application number | Description | Published |
|---|---|---|
| 20090318579 | Method for Depolymerizing Polyester and Unsaturated Polyester, and Method for Recovering Polyester Monomer Using the Depolymerization - A method for rapidly depolymerizing a polyester and an unsaturated polyester by irradiating the polyester with microwaves in the presence of an alkylene glycol in which a titanium oxide fine powder having a bulk density of not more than 0.3 g/cm | 12-24-2009 |
Kazuyuki Ikenaga, Tachikawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20110303844 | ELECTRON MICROSCOPE, AND SPECIMEN HOLDING METHOD - It is an object of the present invention to provide an electron microscope for properly applying a retarding voltage to a sample which is brought into electrical conduction. | 12-15-2011 |
Masanori Ikenaga, Kobe-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090273125 | MANUFACTURING APPARATUS AND MANUFACTURING METHOD FOR TUBULAR RESIN FILM - A manufacturing apparatus and manufacturing method are provided for manufacturing stably from a thermoplastic resin a resin film product having a small and uniform thickness and smooth surfaces, which has been impossible with a conventional tube extruding method or and blown film extrusion method. It comprises a heating extruder ( | 11-05-2009 |
Masanori Ikenaga, Hyogo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090294033 | Device and method for cutting and winding a tubular resin film - A device and method are provided for continuously manufacturing a thermoplastic resin film product of any width having a small film thickness and uniform flat surface at an excellent yield. | 12-03-2009 |
Osamu Ikenaga, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20080232671 | MASK PATTERN VERIFYING METHOD - A mask pattern verifying method include obtaining first information about a hot spot from design data of a mask pattern, obtaining second information about the mask pattern actually formed on a photo mask, and determining a measuring spot of the mask pattern actually formed on the photo mask, based on the first and second information. | 09-25-2008 |
| 20090046280 | MASK DEFECT INSPECTION DATA GENERATING METHOD, MASK DEFECT INSPECTION METHOD AND MASK PRODUCTION METHOD - According to a mask defect inspection data generating method, a distance between inspection areas neighboring in a predetermined direction is calculated based on inspection area control information defined in photomask inspection data. It is determined whether or not the calculated distance between inspection areas is less than a predetermined distance. When it is determined that the distance between inspection areas is less than a predetermined distance, the inspection area is combined to produce an optimization inspection area. The produced optimization inspection area information is defined in inspection layout data for making a reference in die-to-database defect inspection. | 02-19-2009 |
| 20090162758 | PHOTOMASK HAVING CODE PATTERN FORMED BY CODING DATA CONVERSION PROCESS INFORMATION, PHOTOMASK FORMATION METHOD, AND SEMICONDUCTOR DEVICE FABRICATION METHOD - Design data of a wafer pattern to be formed on a semiconductor wafer is converted into mask data corresponding to a mask pattern to be formed on a photomask for use in the formation of the wafer pattern, and the mask pattern is formed on the photomask on the basis of the mask data. A code pattern obtained by coding information of the data conversion process of converting the design data into the mask data is formed on the photomask. | 06-25-2009 |
| 20090202924 | METHOD OF EVALUATING A PHOTO MASK AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of evaluating a photo mask, includes measuring each dimension of a plurality of pattern portions of a mask pattern formed on a photo mask, obtaining an inter-pattern distance between the pattern portion and a pattern different from the pattern portion with respect to each of the pattern portions, obtaining a dimensional difference between the measured dimension of the pattern portion and a target dimension of the pattern portion with respect to each of the pattern portions, grouping the dimensional difference obtained for each pattern portion into a plurality of groups in accordance with the inter-pattern distance obtained for each pattern portion, obtaining an evaluation value based on the dimensional difference in each group with respect to each of the groups, and evaluating the photo mask based on the evaluation value. | 08-13-2009 |
Shuji Ikenaga, Nara JP
| Patent application number | Description | Published |
|---|---|---|
| 20110317431 | Optical Element, Method for Manufacturing Optical Element, Light Emitting Unit, and Method for Assembling Light Emitting Unit - Provided are an optical element and a method for manufacturing the optical element, wherein the concave optical surface of the optical element does not adhere to the metal mold convex surface and excellent mold releasability is ensured by providing the end surface of the optical element with an end section which is continuous to the outer end section of the concave optical surface of the optical element and providing the end section with a tapered section having a tilt with respect to the flat surface formed by the outer end section of the concave optical surface at the time of forming the optical element by means of a liquid drop method. The tapered section can be used for alignment at the time of assembling the light emitting unit, and contributes to process time reduction and prevention of generation of failures. | 12-29-2011 |
Takayuki Ikenaga, Wakayama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100305254 | SURFACTANT COMPOSITION FOR EMULSION POLYMERIZATION - The present invention provides a surfactant composition for emulsion polymerization containing an alkyl ether sulfate represented by formula (1) and a method for producing a polymer emulsion including emulsion polymerization of a monomer in the presence of the surfactant composition for emulsion polymerization: | 12-02-2010 |
Yoshifumi Ikenaga, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20100295530 | Power supply voltage control circuit - A power supply voltage control circuit controls power supply voltage supplied to a target circuit that performs certain signal processing. The power supply voltage control circuit includes a control signal generation circuit that selectively generates first and second control signals when the power supply voltage supplied to the target circuit is increased from a first power supply voltage to a second power supply voltage, the second power supply voltage being higher than the first power supply voltage, and a power supply circuit that increases the power supply voltage toward a voltage level of the second power supply voltage based on the first control signal, or increases the power supply voltage to a voltage level higher than the second power supply voltage first and subsequently decreases the power supply voltage to the second power supply voltage based on the second control signal. | 11-25-2010 |
| 20110068855 | Semiconductor integrated circuit device and method for controlling power supply voltage - The present invention is a semiconductor integrated circuit device including a target circuit, a voltage supply circuit that supplies the power supply voltage to the target circuit, a control circuit that controls an output voltage of the voltage supply circuit, and a target voltage prediction circuit that predicts a voltage value of the power supply voltage. The control circuit changes the output voltage of the voltage supply circuit by a predetermined voltage value. The target voltage prediction circuit detects a change amount of an operating frequency of the target circuit along with the change of the predetermined voltage value, and calculates a target voltage value based on a relation between the change amount of the operating frequency and the predetermined voltage value. The voltage supply circuit supplies a power supply voltage corresponding to the target voltage value to the target circuit. | 03-24-2011 |
| 20110187419 | SEMICONDUCTOR INTEGRATED CIRCUIT AND VOLTAGE CONTROLLER THEREWITH - A semiconductor integrated circuit is capable of accurately detecting the characteristics of a chip. The semiconductor integrated circuit includes a monitor circuit and a control circuit. The control circuit generates a clock pulse signal having M successive pulses (M is 2 or a greater integer), and outputs the clock pulse signal to the monitor circuit. The monitor circuit includes a frequency divider and a ring oscillator. The frequency divider frequency divides the clock pulse signal by M and generates the resulting signal as an enable signal. The ring oscillator generates an oscillation signal as a monitor output value during a period defined in accordance with the enable signal. | 08-04-2011 |
| 20110241725 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When an operation of a specified one of monitor circuits is defective or any of elements forming a ring oscillator in each of the monitor circuits has characteristic abnormality, if voltage control is performed based on a result from the monitor operating at a lowest speed, a required voltage may be overestimated. This results in an increase in power consumption, and also causes an accuracy reduction when the average value of detection results from the multiple monitors is calculated. The multiple monitor circuits are provided. Of the detection results therefrom, any detection result falling outside a predetermined range is ignored, and the average value of the remaining monitor results is used as a final monitor detection value. | 10-06-2011 |