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Ikeda, Kawasaki
Hirokazu Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20080244580 | Redundant configuration method of a storage system maintenance/management apparatus - Provided is a method of managing a computer system including a plurality of storage systems and a plurality of management appliances for managing the plurality of storage systems. A first management appliance and a second management appliance hold an identifier of a first storage system and management data obtained from the first storage system. The method includes the steps of: selecting a third management appliance from the plurality of management appliances when a failure occurs in the first management appliance; transmitting the identifier held in the second management appliance from the second management appliance to the selected third management appliance; and holding the identifier transmitted from the second management appliance in the selected third management appliance. Thus, it is possible to prevent, after failing-over due to an abnormality of a maintenance/management appliance, a single point of failure from occurring to reduce reliability of the maintenance/management appliance. | 10-02-2008 |
| 20110047410 | REDUNDANT CONFIGURATION METHOD OF A STORAGE SYSTEM MAINTENANCE/MANAGEMENT APPARATUS - Provided is a method of managing a computer system including a plurality of storage systems and a plurality of management appliances for managing the plurality of storage systems. A first management appliance and a second management appliance hold an identifier of a first storage system and management data obtained from the first storage system. The method includes the steps of selecting a third management appliance from the plurality of management appliances when a failure occurs in the first management appliance; transmitting the identifier held in the second management appliance from the second management appliance to the selected third management appliance; and holding the identifier transmitted from the second management appliance in the selected third management appliance. Thus, it is possible to prevent, after failing-over due to an abnormality of a maintenance/management appliance, a single point of failure from occurring to reduce reliability of the maintenance/management appliance. | 02-24-2011 |
Katsuhiko Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090231824 | Plug-in unit-mounting structure and electronic apparatus - A plug-in unit-mounting structure which makes it possible to efficiently accommodate plug-in units without being dependent on the structure of a shelf. The plug-in unit-mounting structure comprises a shelf that has connectors disposed on a back wiring board, for being fitted to the plug-in units, and at least one mounting frame that is mounted in the shelf, for each accommodating an associated one of the plug-in units, and enabling the plug-in unit to be inserted in and removed from an associated one of the connectors, the mounting frame being provided with a guide rail which enables a position of disposition of the plug-in unit to be changed according to a size of the plug-in unit. This makes it possible to efficiently accommodate plug-in units without being dependent on the structure of a shelf. | 09-17-2009 |
| 20100103633 | CASE OF AN ELECTRONIC DEVICE - A case for an electronic device includes a printed circuit board; a frame capable of storing the printed circuit board; a back board equipped on a back side of the frame, and including a connector for connecting the printed circuit board; rail holders equipped in predetermined positions of the frame and extending from a front side of the case to the back board; and guide rails engaged with the rail holders respectively and including engagement parts capable of engaging with the rail holders respectively, and holding parts for holding both ends of the frame, and extending in accordance with the rail holders, respectively. | 04-29-2010 |
Katsuhiro Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090129498 | MIMO DEMODULATOR AND METHOD FOR THE SAME - Channel estimates calculated by a channel estimator ( | 05-21-2009 |
Kazuto Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100022080 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes nitridizing a silicon substrate with ammonia while heating the silicon substrate, then heating the silicon substrate in an atmosphere containing nitrogen and oxygen to form a gate insulating film including a silicon-based insulating film containing nitrogen and oxygen, then annealing the silicon substrate in an oxygen atmosphere, and forming a gate electrode on the gate insulating film. | 01-28-2010 |
Keiji Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20110045663 | Field-effect transistor and method for fabricating the same - A field-effect transistor that increases the operation speeds of complementary field-effect transistors. Each of an nMOSFET and a pMODFET has a Ge channel and source and drain regions formed of an NiGe layer. The height of Schottky barriers formed at a junction between a channel region and the source region of the nMOSFET and at a junction between the channel region and the drain region of the nMOSFET is changed by very thin high-concentration segregation layers formed by making As atoms, Sb atoms, S atoms or the like segregate at the time of forming the NiGe layer. As a result, Schottky barrier height suitable for the nMOSFET and the pMODFET can be obtained, this being capable of realizing high-speed CMOSFETS. | 02-24-2011 |
Kiyohiko Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090262494 | INFORMATION PROCESSING DEVICE AND DISPLAY DEVICE - An information processing device has: a support stand having a base that lies flat and a pole that stands on the base; a processing unit that performs data processing; a display panel that displays an image; and a storage unit that stores information. The device further has an adaptor that supports the processing unit and the storage unit, when the adaptor is attached to the support stand. The adaptor also supports the display panel such that the processing unit and the storage unit are hidden behind the display panel. | 10-22-2009 |
| 20110038117 | INFORMATION PROCESSING DEVICE AND DISPLAY DEVICE - An information processing device has: a support stand having a base that lies flat and a pole that stands on the base; a processing unit that performs data processing; a display panel that displays an image; and a storage unit that stores information. The device further has an adaptor that supports the processing unit and the storage unit, when the adaptor is attached to the support stand. The adaptor also supports the display panel such that the processing unit and the storage unit are hidden behind the display panel. | 02-17-2011 |
| 20110227800 | DISPLAY DEVICE HAVING AN ANTENNA AND METHOD OF MANUFACTURING SAME - A display device and a method of manufacturing the same, the display includes: an electrode plate operable to have a radio-frequency wave to pass therethrough; a light-emitting portion disposed in a direction of one surface of the electrode plate, the light-emitting portion including the electrode plate serving as a back electrode; and an antenna disposed in a direction of another surface of the electrode plate, the antenna having a stripline structure or a microstrip line structure and using a potential of the electrode plate as a reference potential. | 09-22-2011 |
Mamoru Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100289684 | ANALOG-DIGITAL CONVERTER CIRCUIT AND ANALOG-DIGITAL CONVERSION METHOD - Provided is an analog-digital converter circuit including: a comparison unit that sequentially compares an analog input voltage with reference voltages, which sequentially vary, and outputs a comparison result as a digital value; a standard voltage generation unit that generates a standard voltage for correcting the reference voltages; a storage unit that stores a comparison result of the standard voltage obtained by the comparison unit; and a reference voltage generation unit that generates the reference voltages based on the comparison result of the standard voltage. | 11-18-2010 |
Mitsutoshi Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100040071 | COMMUNICATION SYSTEM - A communication system for performing communications on a network, including: a user terminal; and an edge node disposed at an edge of a provider domain and having a transfer control portion for controlling forwarding of packets forwarded from an originating user terminal or packets forwarded from another edge node. When definitions of important flow packets are set in the edge node, the transfer control portion establishes a connection for transfer of important flow packets between an edge node with which the originating user terminal is connected and an edge node with which a destination user terminal is connected. | 02-18-2010 |
Motohisa Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100117714 | Semiconductor Integrated Circuit - A semiconductor integrated circuit that carries out intermittent operation, includes a processor block; an logical operation block other than a processor; a first switch part configured to supply a normal operation voltage to the logical operation block other than a processor; a second switch part configured to supply the normal operation voltage to the processor block; a third switch part configured to supply a data holding voltage lower than the normal operation voltage to the processor block; and a fourth switch part configured to be turned on, when the second switch means is turned off and the third switch means is turned on, and supply the data holding voltage to the processor block. | 05-13-2010 |
Norihiro Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090132893 | RECEIVING DEVICE AND DECODING METHOD THEREOF - A receiving device in a communication system that separates one frame of information bits into plural blocks, performs turbo encoding of the information bits of each block and transmits the result, and decodes the encoded information bits, where the receiving device includes plural decoders number of which is less than the number of blocks per frame. Each decoder performs a decoding process on encoded information bits of each block that have been expressed by likelihood, when a condition for stopping decoding is met, executes the decoding process of encoded information bits of another block for which decoding has not yet been performed. When the condition for stopping decoding has been met for all block before the number of times decoding has been performed for each decoder reaches a preset maximum number of repetitions, the decoding results of all the blocks are serially combined, an error detection process is executed, and when no error is detected, the decoding results are output. | 05-21-2009 |
| 20100138725 | ERROR DETECTION DEVICE, ERROR CORRECTION/ERROR DETECTION DECODING DEVICE AND METHOD THEREOF - Error detection that detects an error in an input data sequence, the input data sequence created by regarding a data sequence having a specified bit length as a polynomial, dividing that polynomial by a generator polynomial for generating error detection code and adding the error detection code to the data sequence so the remainder becomes ‘0’. Including calculating remainder values by dividing polynomials that correspond to each respective bit position by the generator polynomial and saving those remainder values; inputting together with an input data sequence, bit position information that indicates proper bit position of each data of the input data sequence, finding remainder values that correspond to proper bit positions of data of the input data sequence that are not ‘0’, performing bit-corresponding addition of each of the found remainder values; and determining no error in the input data sequence when all bits of the addition result become ‘0’. | 06-03-2010 |
Noriko Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20120002844 | Computer product, information display apparatus, and information display method - A 3-dimesional model of an antigen is regarded as a display subject and a 3-dimesional model of an antibody is regarded as a comparison subject. A portion of the molecular surface of the display subject at a distance enabling binding with the comparison subject is cut out as a display surface. The 3-dimensional model of the antigen, which is the display subject, is displayed in a rotated state, where the normal of the display surface is rotated to point in a counter viewing direction, whereby the 3-dimensional model is rotated in a viewing coordinate system. The display surface alone is displayed in color, whereas other portions of the molecular surface are not, thereby enabling the display surface of the antigen that is at a distance enabling binding with the antibody to be displayed at a position easily viewed by the user. | 01-05-2012 |
Noriyuki Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090064065 | Method of verifying circuit and computer-readable storage medium for storing computer program - A method of verifying a circuit for use in an apparatus for verifying a circuit operation indicated by circuit information, the circuit including a plurality of logic circuits and at least one connection line between the logic circuits, the method includes: obtaining information of a plurality of pieces of asynchronous circuits from the circuit information; determining information of asynchronous circuits of a first type and a second type stored in a library; extracting information of an asynchronous circuit of a third type including the asynchronous circuits of the first type and the second type; and extracting verification information associated with the information of the asynchronous circuit of the third type, for verifying the circuit. | 03-05-2009 |
Takuro Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20080215232 | Driving assist system and vehicle-mounted apparatus - There is provided a driving assist system comprising: a road side apparatus which transmits the traffic circumstance information; and a vehicle-mounted apparatus including: an outputting part which outputs driving assist information for assisting a driving operation on the basis of output data on the basis of the at least one kind of the traffic circumstance information; and a controller for: generating the output data for outputting the driving assist information based on the traffic circumstance information; determining whether the output data is valid; and selecting one the output data which is determined as valid, on the basis of a predetermined standard validity, wherein the outputting part outputs the driving assist information using the selected output data. | 09-04-2008 |
| 20110054874 | DISTRIBUTED PROCESSING-TYPE SIMULATOR - A simulator simulates the behavior of a plurality of agents existing in the virtual space. Each of a plurality of calculators, communicable with one another, includes a space allocation storage that stores space allocation information, a space allocation control part that updates the space allocation information, an allocation change candidate space extracting part that extracts a divided space to be a candidate for the allocation change, a communication amount estimating part that calculates an amount of communication or an amount of change in communication generated between calculators based on the number of agents, a space allocation change judging part that determines whether or not to allocate a divided space to another calculator based on the amount of communication or the amount of change in communication, and a space allocation change executing part that requests the space allocation control part and other calculators to change the space allocation. | 03-03-2011 |
| 20110130964 | DRIVE ASSIST APPARATUS, METHOD, AND RECORDING MEDIUM - A drive assist apparatus includes: a road-information storage unit storing road information; a traffic-signal information storage unit to store information regarding a traffic-signal change timing; a receiving unit to receive other-vehicle information; an obtaining unit to obtain host-vehicle information; a determining unit to determine whether the other vehicle becomes an obstacle to the host vehicle; and a calculating unit to calculate a recommended speed based on the host-vehicle information, the road information, and information regarding the traffic-signal change timing, when the other vehicle is determined to not become an obstacle to the host vehicle, and calculate the recommended speed based on the host-vehicle information, the road information, the information regarding the traffic-signal change timing, and an arrival delay time for avoiding an obstacle caused by the other vehicle, when the other vehicle is determined to become the obstacle to the host vehicle. | 06-02-2011 |
| 20110313740 | VEHICLE BEHAVIOR ESTIMATION DEVICE - A vehicle behavior estimation device includes: a storage unit configured to store a restriction condition at a point of a vehicle for which behavior is estimated; vehicle state data that includes position information and speed information of the vehicle; behavior parameters that include speed information and acceleration information of the vehicle; and physical restriction conditions that include an upper limit and a lower limit of the acceleration information; and a processor configured to obtain the vehicle state data by using the restriction condition at the point; calculate behavior parameters of a vehicle model that satisfy a physical restriction condition from the vehicle state data and the restriction condition at the point; update the vehicle state data of the vehicle model based on the behavior parameters; and repeat processing to calculate behavior parameters by using the updated vehicle state data and to update the vehicle state data. | 12-22-2011 |
Tetsu Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20110222496 | METHOD FOR OPERATING A MULTI-CELL RADIO SYSTEM AND A MULTI-CELL RADIO SYSTEM - For enhancing user throughput and coverage within a multi-cell radio system a method for operating a multi-cell radio system, especially an OFDMA-based radio system including a plurality of base stations, wherein different frequency reuse factors are used within different reuse zones of one cell by a fractional frequency reuse (FFR) scheme, the method includes the following steps: allocating a size or resource to the different reuse zones, and allocating users into different reuse zones. Further, a multi-cell radio system is described, preferably for carrying out the above mentioned method. | 09-15-2011 |
Toru Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090296262 | FLYING HEIGHT CONTROL METHOD AND CIRCUIT - A method of the present invention is used to control a flying height of a head operable to read data from and write data to a disk of a recording medium housed in an enclosure. In this method, the head is positioned to a predetermined radial measurement location on the disk to obtain error information on errors in the positioning of the head. A frequency analysis is performed on the obtained error information. Disturbance information on errors caused by a wind disturbance is calculated from the frequency analysis result. Pressure information on an air pressure in the enclosure is calculated based on the calculated disturbance information. A control value for controlling a flying height of the head with respect to the disk is determined based on the calculated pressure information. The flying height of the head is controlled based on the determined control value. | 12-03-2009 |
| 20100134913 | FREQUENCY CONTROL APPARATUS AND STORAGE DEVICE - According to one embodiment, a frequency control apparatus includes an eccentric component storage module, a frequency correction amount calculating module, and an oscillator control module. The eccentric component storage module stores in advance an eccentric component calculated by a discrete Fourier transform of the number of clock signals measured for each servo frame. The frequency correction amount calculating module calculates the number of clock signals corresponding to the servo frame based on the eccentric component stored in the eccentric component storage module and calculates a frequency correction amount corresponding to the servo frame based on the number of clock signals. The oscillator control module controls the operation of a frequency oscillator such that a frequency for oscillating a clock signal in the frequency oscillator is adjusted according to the frequency correction amount calculated by the frequency correction amount calculating module. | 06-03-2010 |
Yoshiro Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20080239967 | NETWORK PERFORMANCE ESTIMATING DEVICE, NETWORK PERFORMANCE ESTIMATING METHOD AND STORAGE MEDIUM HAVING A NETWORK PERFORMANCE ESTIMATING PROGRAM STORED THEREIN - A network performance estimating device for estimating network performance of a parallel computing machine for executing plural processes in parallel, includes a communication data obtaining unit that obtains communication data output from plural calculation nodes when the plural processes are executed by using the plural calculation nodes, a design estimating unit for referring to a design information storing unit that stores design information defining a network as an estimation target to execute a simulation on communications when the communication data obtained by the communication data obtaining unit are transmitted through the network as the estimation target, and renews estimation information representing an estimation result of the estimation target network stored by an estimation information storing unit on the basis of the obtained simulation result, and a communication data transmission unit for transmitting the communication data obtained by the communication data obtaining unit to an addressed calculation node. | 10-02-2008 |
Yoshiyuki Ikeda, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090265917 | METHOD OF MANUFACTURING THIN FILM MAGNETIC HEAD - By the method of manufacturing a thin film magnetic head, a magnetic material having a suitable characteristic can be used for manufacturing a magnetic pole and corrosion of the magnetic pole can be prevented. The method comprises: a step of forming a multilayered magnetic pole; a step of forming a stopper layer on the magnetic pole; a step of forming an insulating layer on the stopper layer; a step of polishing the insulating layer, by chemical mechanical polishing process, until an upper face of the stopper layer is exposed; a step of removing the stopper layer, by dry etching process with a reactive gas, until an upper face of the magnetic head is exposed; a step of removing the upper face of the magnetic pole, by dry etching process with an inert gas, until reaching a prescribed depth; and a step of polishing the upper face of the magnetic pole, by chemical mechanical polishing process, until the upper face of the magnetic pole is flattened. | 10-29-2009 |