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Ikarashi, Tokyo

Kazuaki Ikarashi, Tokyo JP

Patent application numberDescriptionPublished
20080285180MAGNETIC SENSING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - An underlying layer is composed of Co—Fe—B that is an amorphous magnetic material. Thus, the upper surface of the underlying layer can be taken as a lower shield layer-side reference position for obtaining a gap length (GL) between upper and lower shields, resulting in a narrower gap than before. In addition, since the underlying layer has an amorphous structure, the underlying layer does not adversely affect the crystalline orientation of individual layers to be formed thereon, and the surface of the underlying layer has good planarizability. Accordingly, PW50 (half-amplitude pulse width) and SN ratio can be improved more than before without causing a decrease in rate of change in resistance (Δ R/R) or the like, thereby achieving a structure suitable for increasing recording density.11-20-2008

Nobuyuki Ikarashi, Tokyo JP

Patent application numberDescriptionPublished
20080203500Semiconductor device and production method therefor - A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a sidewall including, as a constituting material, silicon oxide on a lateral face side of the gate electrode, wherein a silicon nitride film is interposed between the sidewall and at least the lateral face of the gate electrode. This semiconductor device, although having a fine structure with a small gate length, is capable of low power consumption and fast operation.08-28-2008
20090170252Formation method of metallic compound layer, manufacturing method of semiconductor device, and formation apparatus for metallic compound layer - A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.07-02-2009
20090203208COPPER ALLOY FOR WIRING, SEMICONDUCTOR DEVICE, METHOD FOR FORMING WIRING, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A wiring metal contains a polycrystal of copper (Cu) as a primary element and an additional element other than Cu, and concentration of the additional element is, at crystal grain boundaries composing the Cu polycrystal and in vicinities of the crystal grain boundaries, higher than that of the inside of the crystal grains. The additional element is preferably at least one element selected from a group consisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag. This Cu wiring is formed by forming a Cu polycrystalline film, forming an additional element layer on this Cu film, and diffusing this additional element from the additional element layer into the Cu film. This copper alloy for wiring is preferred as metal wiring formed for a semiconductor device.08-13-2009
20090267163Semiconductor Device - According to the present invention, a semiconductor device having a field effect transistor is provided. The field effect transistor comprises a gate insulating film 10-29-2009
20100219478MOSFET, METHOD OF FABRICATING THE SAME, CMOSFET, AND METHOD OF FABRICATING THE SAME - The present invention provides an NMOSFET including a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the gate insulating film. The first gate electrode is composed of silicide of a metal M, and at least one element selected as an impurity from a group consisting of sulfur (S), fluorine (F) and chlorine (Cl). The impurity exists as an impurity layer at a surface of the first gate electrode at which the first gate electrode makes contact with the gate insulating film.09-02-2010
20100320520DIELECTRIC, CAPACITOR USING DIELECTRIC, SEMICONDUCTOR DEVICE USING DIELECTRIC, AND MANUFACTURING METHOD OF DIELECTRIC - To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1−x):x where 0.01≦x≦0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.12-23-2010
20110018100CAPACITOR, SEMICONDUCTOR DEVICE COMPRISING THE SAME, METHOD FOR MANUFACTURING THE CAPACITOR, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1−x): x (0.01≦x≦0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.01-27-2011

Patent applications by Nobuyuki Ikarashi, Tokyo JP

Takahiro Ikarashi, Tokyo JP

Patent application numberDescriptionPublished
20100250841Memory controlling device - A memory controlling device includes: a request generating section; a row selecting information retaining section; a column selecting information retaining section; a memory bank information managing section; a command generating section; and a command aligning section.09-30-2010
20100281232MEMORY CONTROLLING DEVICE AND MEMORY CONTROLLING METHOD - Disclosed herein is a memory controlling device including: an address converting section configured to convert a logical address included in a request issued from a plurality of clients into a physical address of a memory; a request dividing section configured to divide a converted request converted by the address converting section by a command unit for the memory on a basis of the physical address of the converted request; and an arbitrating section configured to perform arbitration on a basis of the physical address indicated in a divided request output from the request dividing section.11-04-2010