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Ieong
Iat In Ao Ieong, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20120025925 | COMMON MODE NOISE SUPPRESSION CIRCUIT - A common mode noise suppression circuit applicable to differential signal transmission performs common mode noise suppression with respect to differential signals transmitted by a transmission line. An inductance-capacitance resonant structure is formed based on electromagnetic coupling combining a ground structure to suppress common mode noise of differential mode signals at broadband meanwhile keeping low loss of the differential mode signals at broadband via differential transmission lines. By this, the common mode noise suppression circuit performs broadband suppression with related to the common mode noise within frequency scope of several GHzs without affecting the differential mode signals and improves manufacturing process miniaturization to decrease cost. | 02-02-2012 |
Man-Fai Ieong, Miao-Li TW
| Patent application number | Description | Published |
|---|---|---|
| 20080266234 | Shift register and liquid crystal display using same - An exemplary shift register includes plural shift register units (S | 10-30-2008 |
Meikei Ieong, Baoshan Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20080303090 | SUPER HYBRID SOI CMOS DEVICES - The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region. | 12-11-2008 |
| 20090212329 | SUPER HYBRID SOI CMOS DEVICES - The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region. | 08-27-2009 |
Samuel Ieong, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100153388 | METHODS AND APPARATUS FOR RESULT DIVERSIFICATION - Methods, apparatus, and systems directed to receiving search queries, retrieving documents, computing the number of categories to present for a given query, computing the number of results to show in each category, computing an ordering of categories, and for all the result pages beyond the first page employing user interface elements that optionally allow the user to quickly zoom in on a specific category and get more results belonging to that category. | 06-17-2010 |
| 20100250333 | OPTIMIZING CASHBACK RATES - A method, system, and medium are provided for determining optimal sales rebate rates. Historical data, including sales data, price data, and rebate data are received, along with ongoing current data from current rebate transactions. Changes across the spectrum of data are determined and calculations are used to obtain an optimal sales rebate rate for one of more products or services utilizing statistical models, including but not limited to, a linear rebate rate model and a logarithmic-linear rebate rate model for one or more products or services. A mathematical analysis determines the appropriate model to use to obtain the optimal sales rebate rate. The optimal sales rebate rate may be applied to computing or non-computing environments, in whole or as a combination of both computing and non-computing environments. | 09-30-2010 |
| 20100287060 | PROVIDING TIME-SENSITIVE INFORMATION FOR PURCHASE DETERMINATIONS - A method, system, and medium are provided that are directed to providing a user with time-sensitive information that is usable to determine when to purchase a product. In accordance with embodiments of the technology, exemplary steps include using historical product information to generate time-sensitive information. Moreover, in response to receiving from a user a request to receive information describing a given product, time-sensitive information is caused to be presented. For example, time-sensitive information might be usable by the user to determine when to purchase the given product and an alternative product. | 11-11-2010 |
Samuel Ieong, Mountain View, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110184802 | AUCTION FORMAT SELECTION USING HISTORICAL DATA - An auction format may be selected pursuant to analyzing and identifying certain statistical patterns in historical data. For example, the choice of auction format may be based on whether bids and quality exhibit correlation, which can be identified in the historical data. By identifying the statistical patterns in the data, one can choose an auction format that can achieve generation of higher revenue. Such techniques allow an auctioneer, such as a search engine, to generate higher revenue than using a fixed auction format. For example, in the context of sponsored search auction, if the value of a click and the probability of a click are positively correlated, the auctioneer generates higher revenue by ranking the advertisers by bids rather than by bids multiplied by quality. | 07-28-2011 |
| 20110307517 | RELAXATION FOR STRUCTURED QUERIES - A structured query may specify attribute values for attributes. An estimate of the number of items that will match the structured query if it is applied to a structured database is determined. If the estimated number of items is below a threshold, the structured query may be relaxed to form new candidate structured queries. The number of candidate queries may be determined based on a desired running time. Each of the candidate structured queries may be determined by changing one or more attribute values of the attributes of the structured query. Estimates of the number of items each of the candidate structured queries will match is determined, and the candidate structured query that has the highest matching estimation is used to query the database. The matching results may be output. | 12-15-2011 |
Tou Ieong, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100183013 | PACKET PROCESSING DEVICE AND METHOD - A packet processing device is provided, which is applied to a network equipment that transmits packets. The device includes: a control module for executing a control schedule; a capture module for capturing at least one packet according to the control schedule; and a disassembling module for disassembling the header of the packet according to the control schedule so as to obtain packet header information. The packet processing device of the present invention can be installed in any network equipment to disassemble and process packets before they are captured by CPUs or memories of back-end computers, thereby achieving rapid processing of packets and reducing usage of CPU resources and occupancy of memories. | 07-22-2010 |