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Idei, JP
Hideomi Idei, Yokohama JP
| Patent application number | Description | Published |
|---|---|---|
| 20090112798 | COMPUTER SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION OF STORAGE SYSTEM - A disk rotation control part for controlling the rotations of a plurality of disk devices is provided. The configuration is such that a disk of a disk device for which an access will not be generated is rotated at a second rate of speed, which is faster than 0, and slower than a first rate of speed, which is the rotation speed at access time. DB management information comprises information denoting which DB schema inside a DB is stored in which location. The disk rotation control part, based on a query plan of a query received by the DBMS, and DB management information, specifies the storage location of a DB schema to be accessed when this query is processed, and rotates a disk of the disk device comprising the specified storage location at a first rate of speed. | 04-30-2009 |
Hideomi Idei, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20080301151 | COMPUTER SYSTEM AND DATABASE MANAGEMENT METHOD USING THE SAME - A pre-fetch server, which is connected to a DB server running a DBMS and to a storage apparatus storing DB data, stores information required for judging whether or not a pre-fetch is effective. Judgment on whether or not the pre-fetch will be effective is performed when a pre-fetch I/O is issued. If the pre-fetch server judges that the pre-fetch will be effective, it issues the pre-fetch I/O to the storage apparatus. | 12-04-2008 |
| 20090112894 | Method of reducing storage power consumption by use of prefetch and computer system using the same - Provided is a computer system including: a computer running as a DB server; a storage system including a plurality of disk drives for storing data; and a management module, in which: at least one of the plurality of disk drives stores data of a DB schema written by the computer; the management module specifies the DB schema to be accessed based on a received query, transmits, to the storage system, an instruction to copy at least a portion of the data of the specified DB schema from the disk drive to a memory, and transmits, to the storage system, an instruction to control an rpm of the disk drive that stores the data of the specified DB schema; and the storage system controls the rpm of the disk drive based on the instruction. Accordingly, power consumption of the storage system can be reduced even if installed disks increase in number. | 04-30-2009 |
Hiroaki Idei, Shizuoka JP
| Patent application number | Description | Published |
|---|---|---|
| 20120021354 | COLORED CURABLE COMPOSITION, COLOR RESIST, INK-JET INK, COLOR FILTER AND METHOD FOR PRODUCING THE SAME, SOLID-STATE IMAGE PICKUP DEVICE, IMAGE DISPLAY DEVICE, LIQUID CRYSTAL DISPLAY, ORGANIC EL DISPLAY, AND COLORANT COMPOUND AND TAUTOMER THEREOF - A colored curable composition including: at least one selected from the group consisting of a compound represented by the following Formula (1a) and a tautomer thereof; and at least one polymerizable compound, | 01-26-2012 |
Koji Idei, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20120107531 | COATED PRINTING PAPER - A coated printing paper has a favorable offset printability, which can achieve good ink fixing and ink absorption properties even in ink jet printing, which has suitable dot diffusion even when printed by an ink jet printer using pigment ink, and can prevent the occurrence of white lines. The coated printing paper comprises a base paper and a coating layer which is applied to at least one surface of the base paper and contains a pigment and a binder as major components, wherein the base paper comprises a cationic compound, the coating layer contains, as a pigment, 50 parts by mass or more of ground calcium carbonate based on 100 parts by mass of total pigments in the coating layer, and the applied amount of the coating layer is 2.0 g/m | 05-03-2012 |
Mitsushige Idei, Kobe-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100319826 | PNEUMATIC TIRE FOR RUNNING ON ROUGH TERRAIN - A pneumatic tire is provided in the tread portion with tread blocks capable of improving running performance on rough terrain, wherein a degree of circularity Eb of a contour shape of a section of the tread block taken parallel with the top surface of the tread block at a block foot position is more than a degree of circularity Et of a contour shape of the top surface. The degree of circularity is: 4×pi×S/L2, wherein, pi is the circumference ratio, S is an area of the contour shape, and L is a circumferential length of the contour shape. The block foot position is defined as being spaced apart from a tread bottom by 10% of a height of the tread block from the tread bottom. | 12-23-2010 |
Seiichi Idei, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090119566 | TRANSMITTING DATA WITH VARIABLE UNIT FOR PLAYBACK - Provided is a transmitter for continuously and sequentially transmitting data with a variable unit for playback. The transmitter includes an obtaining section, a buffer, a computing section and a transmitting section. The obtaining section sequentially obtains segment data of the data to be transmitted. The buffer stores an error correction code to correct an error caused in the data by transmission. The computing section computes, every time newly obtained segment data reaches a predetermined size, XOR of the error correction code already stored in the buffer and the newly obtained segment data, and then updates the error correction code with the computed XOR. The transmitting section sequentially transmits the obtained segment data, as well as reads from the buffer and transmits the updated error correction code every time the computing section computes XOR for data in a size corresponding to the unit for playback. | 05-07-2009 |
Takashi Idei, Minamitsuru-Gun JP
| Patent application number | Description | Published |
|---|---|---|
| 20090009126 | NUMERICAL CONTROLLER CONTROLLING ACCELERATION AND DECELERATION OF RESPECTIVE CONTROL AXES UP TO COMMAND SPEEDS - Initial speeds in the move commands for respective control axes at servo-on are determined according to parameter setting, or the comparative relationship or difference in speed among the actual speeds of the control axes so that difference in position between the control axes does not increase as the move commands are executed after the servo-on. The actual speeds of the control axes are set as initial speeds in the move commands, and a target axis is specified on the basis of the comparative relationship among their actual speeds and the other control axes are accelerated or decelerated at the acceleration or deceleration rate specified in the move commands to attain the position and speed of the target axis, so that differences in position and speed among the control axes are gradually decreased as the move commands are executed after the servo-on, thereby preventing abrupt speed changes and suppressing mechanical shocks. | 01-08-2009 |
Yasuo Idei, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100289046 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A light emitting device includes: a multilayer body including a light emitting layer made of a semiconductor; a first bonding metal layer attached to the multilayer body; a substrate; and a second bonding metal layer attached to the substrate and bonded to the first bonding metal layer at a bonding interface, at least one of a planar size of the first bonding metal layer on the bonding interface side and a planar size of the second bonding metal layer on the bonding interface side being smaller than a planar size of the substrate. | 11-18-2010 |
Yoji Idei, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090016126 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed. | 01-15-2009 |
| 20090016139 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line. | 01-15-2009 |
| 20090284309 | POWER SUPPLY VOLTAGE DROPPING CIRCUIT IN WHICH NCH (N-CHANNEL) TRANSISTOR IS USED AS OUTPUT STAGE, SEMICONDUCTOR DEVICE, POWER SUPPLY VOLTAGE CIRCUIT, POWER SUPPLY VOLTAGE DROPPING METHOD, AND POWER SUPPLY VOLTAGE OUTPUTTING METHOD - A device includes an N-channel transistor for output, a voltage raising circuit, a voltage dropping circuit, and an amplifier. A power supply voltage that is a first voltage is supplied to one end of the output N-channel transistor, and the other end of the output N-channel transistor functions as an output terminal. The voltage raising circuit raises the first voltage to generate a second voltage higher than the first voltage. The voltage dropping circuit reduces the second voltage to generate a third voltage that is higher than the first voltage and is lower than the second voltage. The amplifier amplifies the difference between a reference voltage and a voltage generated at the output terminal, using the third voltage as a power supply voltage, to generate a fourth voltage, and supplies the fourth voltage to the gate of the N-channel transistor for output. | 11-19-2009 |
| 20100284228 | SEMICONDUCTOR DEVICE HAVING DATA INPUT/OUTPUT UNIT CONNECTED TO BUS LINE - To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fourth banks connected via the first, second, and third buffers to the second bus line; fifth to eighth banks connected via the fourth and fifth buffers to the second bus line; and a data input/output unit connected to the second bus line. Transfer delay times of the fourth and fifth buffers are longer than transfer delay times of the first, second, and third buffers. Thereby, it becomes possible to eliminate differences in data transfer times resulting from differences in distances between far and near ends without causing significant increase in wire density, increase in power consumption, or the like. | 11-11-2010 |