Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Ichise
Masanori Ichise, Scarsdale, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100196274 | Methods for Diagnosing Diseases and Evaluating Treatments Therefor Using Pet - The present invention relates to methods for determining whether a mammal has a disease, such as diabetes, using PET data analysis techniques. These methods include administering to a mammal a PET-compatible tracer, such as a radioligand specific for a vesicular monoamine transporter 2 (VMAT2) receptor, and measuring total functional β-cell capacity (volume) of the mammal's pancreas using PET data analysis techniques. Methods for tracking the efficacy of a treatment for diabetes, for evaluating the regeneration of β-cells in a pancreas, and for monitoring a patient with a transplanted pancreas are also provided. | 08-05-2010 |
Shogo Ichise, Nishikamo-Gun JP
| Patent application number | Description | Published |
|---|---|---|
| 20080236415 | ROTARY STAMP WITH MASTER STAMP - In a rotary stamp with master stamp incorporating a master stamp | 10-02-2008 |
| 20080236416 | ENDLESS PRINT BELT FOR ROTARY STAMP - An endless print belt for rotary stamp in which a plurality of print sections 5 are disposed with spaced-out parts 51 between each other on the surface of a print belt main body 24 at least the surface of which is formed of porous material, wherein a groove 25 in the width direction is formed at an intermediate position of each spaced-out part 51. Preferably, the spaced-out part 51 is formed such that the surface thereof is in non-porous state or both ends of the groove 25 are formed into a band part 53 for preventing ink from running out. | 10-02-2008 |
Teruhisa Ichise, Ome JP
| Patent application number | Description | Published |
|---|---|---|
| 20080237752 | METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented. | 10-02-2008 |
| 20080283970 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 11-20-2008 |
| 20100197105 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 08-05-2010 |
Teruhisa Ichise, Chuo-Ku JP
| Patent application number | Description | Published |
|---|---|---|
| 20090267160 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises an anti-fuse element. The anti-fuse element includes a semiconductor substrate, a first gate insulating film, a first gate electrode, a high-concentration impurity region formed in the semiconductor substrate under the first gate electrode, and first source/drain regions provided in the semiconductor substrate on both sides of the high-concentration impurity region. The first source/drain regions contain an impurity having the same conduction type as conduction type of the high-concentration impurity region. | 10-29-2009 |