Ic Su
Ic Su Oh, Ichon-Si KR
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20100117702 | DUTY CYCLE CORRECTION APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal. | 05-13-2010 |
Ic Su Oh, Icheon-Si KR
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20110292750 | BIT LINE SENSE AMPLIFIER CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A bit line sense amplifier control circuit is configured to drive a bit line sense amplifier according to a first sense amplifier enable signal and a second sense amplifier enable signal, wherein the driving force of the bit line sense amplifier is changed in response to a column selection control signal. | 12-01-2011 |
20140062557 | METHOD FOR REDUCING OUTPUT DATA NOISE OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS IMPLEMENTING THE SAME - Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result. | 03-06-2014 |
Ic Su Oh, Icheon-Si Gyeonggi-Do KR
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20130093490 | INTERNAL VOLTAGE GENERATION CIRCUIT AND METHOD - An internal voltage generation method includes the steps of: setting first to third sections by using a reference voltage; determining to which section an internal voltage level corresponds, among the first to third sections; and generating the internal voltage by controlling a voltage pumping amount according to a section corresponding to the internal voltage level. | 04-18-2013 |
20140140016 | POWER METAL MESH AND SEMICONDUCTOR MEMORY DEVICE AND METHOD INCLUDING THE SAME - A power metal mesh and a semiconductor memory device including the same are provided. As the power metal mesh configured to reduce noise coupling generated between adjacent chips disposed on an interposer, a band stop filter unit including an inductor and a capacitor coupled in parallel is disposed between the adjacent chips to effectively reduce the noise coupling of a specific frequency band generated between the adjacent chips. | 05-22-2014 |
Ic Su Oh, Icheon KR
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20130117477 | WIRELESS SIGNAL TRANSMITTING/RECEIVING APPARATUS FOR SEMICONDUCTOR SYSTEM - A wireless signal transmitting/receiving apparatus for a semiconductor system is disclosed The apparatus includes a serializer/deserializer (SERDES) circuit and a coupling pad. The SERDES circuit outputs a parallel input signal as a serial signal during transmission, and outputs a serial input signal as a parallel signal during reception. The coupling pad generates an inductively coupled wireless signal according to the serial signal outputted from the SERDES circuit, and provides a signal generated by inductive coupling with an external device as the serial input signal of the SERDES circuit. | 05-09-2013 |