Patent application number | Description | Published |
20090079751 | Deep Pixel Display And Data Format - A method, graphics card, system, and data stream for generating a deep pixel display on a display device are provided. A first set of data relating to a region associated with a display is provided. The first set of data is processed to define a pixel definition. A second set of data relating to the first pixel is determined. At least one portion of the first set of data is rearranged to form at least a portion of the second set of data. A deep pixel is defined based upon the second set of data. The present invention also includes a system that includes a display controller that is adapted to define a deep pixel based upon rearranging the portion of the first set of data. | 03-26-2009 |
20090284534 | THERMAL MANAGEMENT OF GRAPHICS PROCESSING UNITS - Some embodiments include a graphics processing with thermal management capabilities. The graphics processing unit may include a display controller, a microprocessing engine coupled to the display controller, and a clock circuit coupled to the display controller and the microprocessing engine. The clock circuit may further include a raw clock signal coupled to the display controller, a divider coupled to the raw clock signal, and a multiplexer coupled to the divider. The divider may generate a divided version of the raw clock signal, which may be coupled to the multiplexer along with the raw clock signal. The multiplexer may selectively provide the raw clock signal and/or the divided version of the clock signal to the microprocessing engine such that the microprocessing engine may receive a timing signal that is independent of operations of the graphics processing unit and result in fewer glitches. | 11-19-2009 |
20100079445 | Method for reducing graphics rendering failures - A method and electronic device employing the method of processing a frame of graphics for display is provided that includes developing a frame in a first software frame processing stage following a first vertical blanking (VBL) heartbeat, issuing a command indicating the first stage is complete, and performing a final software frame processing stage without waiting for a subsequent VBL heartbeat. The method may alternatively include performing the final software frame processing stage regardless as to whether a target framebuffer is available, performing all but final hardware frame processing stages regardless as to whether the target framebuffer is in use, and performing the final hardware processing stage if the target framebuffer is not in use. | 04-01-2010 |
20100082859 | DISPLAYPORT I2C SPEED CONTROL - Circuits, methods, and apparatus that allow a DisplayPort compatible host device to control data transactions over an I | 04-01-2010 |
20100091025 | SEAMLESS DISPLAY MIGRATION - Exemplary embodiments of methods, apparatuses, and systems for seamlessly migrating a user visible display stream sent to a display device from one rendered display stream to another rendered display stream are described. For one embodiment, mirror video display streams are received from both a first graphics processing unit (GPU) and a second GPU, and the video display stream sent to a display device is switched from the video display stream from the first GPU to the video display stream from the second GPU, wherein the switching occurs during a blanking interval for the first GPU that overlaps with a blanking interval for the second GPU. | 04-15-2010 |
20100328323 | VIRTUAL GRAPHICS DEVICE DRIVER - Systems and methods are disclosed to enable switching of graphics processing unit (GPU) resources based on different factors. Embodiments include a virtual graphics driver as an interface between GPU drivers and the applications or graphics framework executing on an electronic device. The virtual graphics driver may switch GPU resources from a first GPU to a second GPU by routing function calls to the first GPU or the second GPU. The switching of GPU resources may be based on power management, system events such as hot-plug events, load management, user requests, any other factor, or any combination thereof. In some embodiments, a virtual frame buffer driver is provided that interfaces with the frame buffer of the GPU and provides a virtual view of the frame buffer to manage additional system application programming interfaces (APIs) during the switch. | 12-30-2010 |
20110023040 | POWER-EFFICIENT INTERACTION BETWEEN MULTIPLE PROCESSORS - A technique for processing instructions in an electronic system is provided. In one embodiment, a processor of the electronic system may submit a unit of work to a queue accessible by a coprocessor, such as a graphics processing unit. The coprocessor may process work from the queue, and write a completion record into a memory accessible by the processor. The electronic system may be configured to switch between a polling mode and an interrupt mode based on progress made by the coprocessor in processing the work. In one embodiment, the processor may switch from an interrupt mode to a polling mode upon completion of a threshold amount of work by the coprocessor. Various additional methods, systems, and computer program products are also provided. | 01-27-2011 |
20110252180 | MEMORY CONTROLLER MAPPING ON-THE-FLY - Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks | 10-13-2011 |
20110252200 | COHERENT MEMORY SCHEME FOR HETEROGENEOUS PROCESSORS - Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity. | 10-13-2011 |
20130009975 | METHOD FOR REDUCING GRAPHICS RENDERING FAILURES - A method and electronic device employing the method of processing a frame of graphics for display is provided that includes developing a frame in a first software frame processing stage following a first vertical blanking (VBL) heartbeat, issuing a command indicating the first stage is complete, and performing a final software frame processing stage without waiting for a subsequent VBL heartbeat. The method may alternatively include performing the final software frame processing stage regardless as to whether a target framebuffer is available, performing all but final hardware frame processing stages regardless as to whether the target framebuffer is in use, and performing the final hardware processing stage if the target framebuffer is not in use. | 01-10-2013 |
20130033504 | Seamless Display Migration - Exemplary embodiments of methods, apparatuses, and systems for seamlessly migrating a user visible display stream sent to a display device from one rendered display stream to another rendered display stream are described. For one embodiment, mirror video display streams are received from both a first graphics processing unit (GPU) and a second GPU, and the video display stream sent to a display device is switched from the video display stream from the first GPU to the video display stream from the second GPU, wherein the switching occurs during a blanking interval for the first GPU that overlaps with a blanking interval for the second GPU. | 02-07-2013 |
20130084003 | Psychovisual Image Compression - Psychovisual image compression techniques are disclosed that compress pixel data by a fixed compression ratio with little or no perceptual loss of detail. In some implementations, a psychovisual compression process is selected among several psychovisual compression processes based on characteristics of the pixel data. Compression is achieved during encoding by discarding psychovisually unnecessary bits from the pixel data. The psychovisual compression processes can be implemented in hardware and operate on scan lines of pixels captured by the image sensor. The psychovisual compression techniques can be used with image compression techniques to compress further the pixel data. | 04-04-2013 |
20130283290 | POWER-EFFICIENT INTERACTION BETWEEN MULTIPLE PROCESSORS - A technique for processing instructions in an electronic system is provided. In one embodiment, a processor of the electronic system may submit a unit of work to a queue accessible by a coprocessor, such as a graphics processing unit. The coprocessor may process work from the queue, and write a completion record into a memory accessible by the processor. The electronic system may be configured to switch between a polling mode and an interrupt mode based on progress made by the coprocessor in processing the work. In one embodiment, the processor may switch from an interrupt mode to a polling mode upon completion of a threshold amount of work by the coprocessor. Various additional methods, systems, and computer program products are also provided. | 10-24-2013 |