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Hyunsu
Hyunsu Cho, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20100097416 | ORGANIC DRY JET PRINTING HEAD, AND PRINTING DEVICE AND METHOD USING THE SAME - Disclosed herein is an organic dry jet printing head and a printing device and method using the same, in which a pattern (thin film) can be formed through the repetitive injection of a high-speed jet by regularly and repeatedly opening and closing an on-off valve in a pattern (thin film) forming region using the on-off valve and a control unit. The organic dry jet printing head and the printing device and method using the same are advantageous in that processes can be performed at atmospheric pressure, a large-area organic electronic device can be manufactured and high-resolution patterns can be printed, thereby improving productivity and economic efficiency. | 04-22-2010 |
Hyunsu Choi, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100214816 | SEMICONDUCTOR DEVICES SUPPORTING MULTIPLE FUSE PROGRAMMING MODES - Semiconductor devices include a plurality of fuses and a plurality of program circuits, respective ones of which are configured to program respective ones of the plurality of fuses. The devices further include a shift register configured to activate at least two of the program circuits. In some embodiments, the shift register includes a first shift register configured to generate first select signals and a second shift register configured to generate second select signals corresponding to data to be programmed to the plurality of fuses. Respective ones of the program circuits may be configured to program respective ones of the fuses responsive to respective pairs of the first select signals and the second select signals. | 08-26-2010 |
| 20100238755 | SEMICONDUCTOR MEMORY DEVICE HAVING POWER SAVING MODE - A semiconductor memory device includes a memory cell array arranged in rows and columns, a row decoder and a control circuit. The row decoder drives word lines connected to the memory cell array by decoding a received row address and being synchronized with an internal clock signal. The control circuit receives a clock signal, a chip select signal and a mode signal, and generates the internal clock signal. The control circuit generates the internal clock signal so that the row decoder does not operate for a predetermined time in response to the chip select signal when the mode signal transitions from a power saving mode to a normal mode. | 09-23-2010 |