| Patent application number | Description | Published |
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| 20080260940 | APPARATUS AND METHOD FOR INTEGRATED SURFACE TREATMENT AND DEPOSITION FOR COPPER INTERCONNECT - A method and system for depositing films on a substrate for copper interconnect in an integrated system is provided. The method includes moving the substrate into a processing chamber having a plurality of proximity heads. Selected ones of the proximity heads is configured to perform at least one of surface treatments and atomic layer depositions (ALDs). The processing chamber is part of the integrated system. Within the processing chamber, barrier layer deposition is performed over a surface of the substrate using one of the plurality of proximity heads functioning to perform barrier layer ALD. In addition, the method includes moving the substrate from the processing chamber, through a transfer module of the integrated system and into a processing module for performing copper seed layer deposition. The processing module for performing copper seed layer deposition is part of the integrated system. Within the processing module for performing copper seed layer deposition, copper seed layer deposition is performed over the surface of the substrate. The integrated system enables controlled-ambient transitions within the integrated system to limit exposure of the substrate to uncontrolled ambient conditions outside of the integrated system. | 10-23-2008 |
| 20080260963 | APPARATUS AND METHOD FOR PRE AND POST TREATMENT OF ATOMIC LAYER DEPOSITION - The embodiments fill the needs of systems and processes that perform substrate surface treatment to provide homogenous, clean, and sometimes activated surface in order to provide good adhesion between layers to improve metal migration and void propagation. In an exemplary embodiment, a proximity head for treating a substrate surface is provided. The proximity head is configured to dispense a treatment gas to treat an active process region of a substrate surface under the proximity head. The proximity head covers the action process region of the substrate surface and the proximity head includes at least one vacuum channel to pull excess treatment gas from a reaction volume between the proximity head and the substrate. The proximity head has an excitation chamber to excite the treatment gas before the treatment gas being dispensed on the active process region portion of the substrate surface. | 10-23-2008 |
| 20080260967 | APPARATUS AND METHOD FOR INTEGRATED SURFACE TREATMENT AND FILM DEPOSITION - The embodiments fill the needs of systems and processes that perform substrate surface treatment to provide homogenous, clean, and sometimes activated surface in order to provide good adhesion between layers to improve metal migration and void propagation. In one exemplary embodiment, a chamber for performing surface treatment and film deposition is provided. The chamber includes a first proximity head for substrate surface treatment configured to dispense a first treatment gas to treat a portion of a surface of a substrate under the first proximity head for substrate surface treatment. The chamber also includes a first proximity head for atomic layer deposition (ALD) configured to sequentially dispensing a first reactant gas and a first purging gas to deposit a first ALD film under the second proximity head for ALD. | 10-23-2008 |
| 20080261412 | APPARATUS AND METHOD FOR ATOMIC LAYER DEPOSITION - The embodiments provide apparatus and methods of depositing conformal thin film on interconnect structures by providing processes and systems using an atomic layer deposition (ALD). More specifically, each of the ALD systems includes a proximity head that has a small reaction volume right above an active process region of the substrate surface. The proximity head small amount of reactants and purging gas to be distributed and pumped away from the small reaction volume between the proximity head and the substrate in relatively short periods, which increases the through-put. In an exemplary embodiment, a proximity head for dispensing reactants and purging gas to deposit a thin film by atomic layer deposition (ALD) is provided. The proximity head is configured to sequentially dispensing a reactant gas and a purging gas to deposit a thin ALD film under the proximity head. The proximity head covers an active process region of a substrate surface. The proximity head also includes at least one vacuum channel to pull excess reactant gas, purging gas, or deposition byproducts from a reaction volume between a surface of the proximity head facing the substrate and the substrate. The proximity includes a plurality of sides, each side being configured to dispense either a reactant gas or a purging gas on the substrate surface underneath the proximity head. Each side has at least one vacuum channel. | 10-23-2008 |
| 20080299772 | Methods of fabricating electronic devices using direct copper plating - The present invention relates to methods and structures for the metallization of semiconductor devices. One aspect of the present invention is a method of forming a semiconductor device having copper metallization. In one embodiment, the method includes providing a patterned wafer having a diffusion barrier for copper; depositing a copperless seed layer on the diffusion barrier effective for electrochemical deposition of gapfill copper. The seed layer is formed by a conformal deposition process and by a nonconformal deposition process. The method further includes electroplating copper gapfill onto the seed layer. Another aspect of the invention includes electronic devices made using methods and structures according to embodiments of the present invention. | 12-04-2008 |
| 20080314756 | Methods and systems for three-dimensional integrated circuit through hole via gapfill and overburden removal - Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes. The deplating component is configured to chemically or to electrochemically remove a portion of the overburden metal formed by the plating component. | 12-25-2008 |
| 20080315418 | Methods of post-contact back end of line through-hole via integration - Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention. | 12-25-2008 |
| 20080315422 | Methods and apparatuses for three dimensional integrated circuits - Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit. | 12-25-2008 |
| 20090113656 | Apparatus for isolated bevel edge clean and method for using the same - An apparatus, system and method for cleaning a substrate edge include a bristle brush unit that cleans bevel polymers deposited on substrate edges using frictional contact in the presence of cleaning chemistry. The bristle brush unit is made up of a plurality of outwardly extending vanes and is mounted on a rotating shaft. An abrasive material is distributed throughout and within the outwardly extending vanes of the bristle brush unit to provide the frictional contact. The bristle brush unit cleans the edge of the substrate by allowing frictional contact of the plurality of abrasive particles with the edge of the substrate in the presence of fluids, such as cleaning chemistry, to cut, rip and tear the bevel polymer from the edge of the substrate. | 05-07-2009 |
| 20090304914 | Self assembled monolayer for improving adhesion between copper and barrier layer - The embodiments fill the need enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect with good electro-migration performance and with reduced risk of stress-induce voiding of copper interconnect. Electromigration and stress-induced voiding are affected by the adhesion between the barrier layer and the copper layer. A functionalization layer is deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect. The functionalization layer forms strong bonds with barrier layer and with copper to improve adhesion property between the two layers. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in order to improve electromigration performance of the copper interconnect is provided. The method includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, and oxidizing a surface of the metallic barrier layer. The method also includes depositing the functionalization layer over the oxidized surface of the metallic barrier layer, and depositing the copper layer in the copper interconnect structure after the funcationalization layer is deposited over the metallic barrier layer. | 12-10-2009 |
| 20090320749 | APPARATUS FOR INTEGRATED SURFACE TREATMENT AND DEPOSITION FOR COPPER INTERCONNECT - An integrated system for depositing films on a substrate for copper interconnect is provided. The system includes a processing chamber with a plurality of proximity heads, and a vacuum transfer module coupled to the processing chamber. Selected ones of the proximity heads are used for surface treatments and atomic layer depositions (ALDs). The system further includes a processing module for copper seed layer deposition, which is integrated with a rinse/dryer to enable dry-in/dry-out process capability and is filled with an inert gas to limit the exposure of the substrate to oxygen. Additionally, the system includes a controlled-ambient transfer module coupled to the processing module for copper seed layer deposition. Further, the system includes a loadlock coupled to the vacuum transfer module and to the controlled-ambient transfer module. The integrated system enables controlled-ambient transitions within the system to limit exposure of the substrate to uncontrolled ambient conditions outside of the system. | 12-31-2009 |
| 20100044867 | METHODS OF POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION - Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention. | 02-25-2010 |
| 20100108491 | METHODS FOR REMOVING A METAL OXIDE FROM A SUBSTRATE - A method for generating plasma for removing metal oxide from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the metal oxide. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an rf field to the cavity using the powered electrode to generate the plasma from the inert and the process gas. | 05-06-2010 |
| 20100181025 | APPARATUS FOR THE REMOVAL OF A FLUORINATED POLYMER FROM A SUBSTRATE - An apparatus generating a plasma for removing fluorinated polymer from a substrate is provided. The apparatus includes a powered electrode assembly, which includes a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The apparatus also includes a grounded electrode assembly disposed opposite the powered electrode assembly so as to form a cavity wherein the plasma is generated. The first wire mesh is shielded from the plasma by the first dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the fluorinated polymer. | 07-22-2010 |
| 20100267229 | METHODS AND SYSTEMS FOR LOW INTERFACIAL OXIDE CONTACT BETWEEN BARRIER AND COPPER METALLIZATION - The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment. | 10-21-2010 |
| 20110065273 | Methods of Fabricating a Barrier Layer Over Interconnect Structures in Atomic Deposition Environments - Methods of depositing a barrier layer on an interconnect structure in an atomic deposition environment are provided. One method includes depositing a barrier layer on the interconnect structure with a first nitrogen concentration during a first phase of deposition in the atomic deposition environment, The interconnect structure is formed in a dielectric layer. Then, continuing the deposition of the barrier layer on the interconnect structure with a second nitrogen concentration during a second phase deposition in the atomic deposition environment. The nitrogen concentration step-wisely decreases from the first nitrogen concentration in the first phase of the barrier layer to the second nitrogen concentration in the second phase of the barrier layer, and the first nitrogen concentration is highest where the barrier layer is in contact with the dielectric layer. A copper layer is then formed over the barrier layer, such that a nitrogen concentration in the barrier layer is lowest where the barrier layer is in contact with the copper layer. | 03-17-2011 |
| 20110143553 | INTEGRATED TOOL SETS AND PROCESS TO KEEP SUBSTRATE SURFACE WET DURING PLATING AND CLEAN IN FABRICATION OF ADVANCED NANO-ELECTRONIC DEVICES - Methods and systems for handling a substrate through processes including an integrated electroless deposition process includes processing a surface of the substrate in an electroless deposition module to deposit a layer over conductive features of the substrate using a deposition fluid. The surface of the substrate is then rinsed in the electroless deposition module with a rinsing fluid. The rinsing is controlled to prevent de-wetting of the surface so that a transfer film defined from the rinsing fluid remains coated over the surface of the substrate. The substrate is removed from the electroless deposition module while maintaining the transfer film over the surface of the substrate. The transfer film over the surface of the substrate prevents drying of the surface of the substrate so that the removing is wet. The substrate, once removed from the electroless deposition module, is moved into a post-deposition module while maintaining the transfer film over the surface of the substrate. | 06-16-2011 |
