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Hyung Wook
Hyung Wook Kim, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110085315 | Ground structure of connector for portable terminal - A ground apparatus for connecting components for a portable terminal suppresses the occurrence of noise by grounding a connector. The ground apparatus includes a connector engaging portion at one side of a main board. A connector that includes a grounding portion is inserted into the connector engaging portion. A shield can is disposed to cover at least at part of the main board. The shield can includes a ground structure formed at the connector engaging portion area to enclose the connector and electrically couple the ground structure with the ground portion of the connector. | 04-14-2011 |
Hyung Wook Lee, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080289861 | Multi-Layer Flexible Printed Circuit Board and Method For Manufacturing the Same - Disclosed are a multi-layer flexible printed circuit board and a method for manufacturing the same. The multi-layer flexible printed circuit board includes an adhesion sheet from which a pressing and heating area is cut, an upper base layer, from which the pressing and heating area is cut, on the adhesion sheet, and a lower base layer under to the adhesion sheet. | 11-27-2008 |
Hyung Wook Moon, Ichon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090046526 | WORD LINE DRIVING CIRCUIT AND METHOD OF TESTING A WORD LINE USING THE WORD LINE DRIVING CIRCUIT - A method of testing a word line using a word line driving circuit comprising: activating a word line by activating a word line driving signal; floating the word line by activating a test mode signal after the activating of the word line; recording data having a predetermined logic value into a memory cell by inputting a write command while the word line is floated; and reading out data from the memory cell by inputting a read command after the recording of data. | 02-19-2009 |
| 20090257300 | FUSE INFORMATION CONTROL DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME, AND CONTROL METHOD THEREOF - A fuse information control device having a delay circuit to delay an active signal, includes a fuse circuit that outputs fuse information in response to a fuse information control signal, and a fuse information control signal generating unit that generates the fuse information control signal in response to one of the active signal and internal delay signals of the delay circuit. | 10-15-2009 |
| 20100061173 | AUTO-REFRESH CONTROL CIRCUIT AND A SEMICONDUCTOR MEMORY DEVICE USING THE SAME - An auto-refresh control circuit includes a control signal generating section configured to simultaneously or individually enable first and second control signals in response to an information combination signal having refresh information and operation mode information and first and second chip selection signals, and an auto-refresh signal generating section configured to generate first and second auto-refresh signals in response to a plurality of command signals and the first and second control signals. | 03-11-2010 |
| 20100091599 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes first and second bank blocks, a mode generator configured to generate a chip select mode signal used to control an operational mode of the first and second bank blocks, and a controller configured to drive the first and second bank blocks in response to the chip select mode signal, first and second select signals, and a predetermined address signal that are used to control driving of the first and second bank blocks, wherein the controller receives the chip select mode signal having a level used to determine a single chip mode to control operation of the first and second bank blocks in one rank unit, and the first and second bank blocks are selectively activated by using the predetermined address signal. | 04-15-2010 |
| 20100097872 | WAFER TEST TRIGGER SIGNAL GENERATING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS, AND A WAFER TEST CIRCUIT USING THE SAME - A wafer test trigger signal generating circuit of a semiconductor memory apparatus includes an enable timing control unit configured to generate an enable signal by using a plurality of address signals, and a trigger signal generating unit configured to generate a test trigger signal, which designates a decoding timing of a test mode defined by the plurality of address signals, in response to the enable signal. | 04-22-2010 |
Hyung Wook Moon, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090185433 | Semiconductor Device - A semiconductor device may include a first logic unit for performing a logic operation with respect to a plurality of first control signals, each of which indicates whether a corresponding one of a plurality of banks of the semiconductor device is in an active state, a refresh detector for outputting a second control signal which is enabled when at least one of the banks performs a self-refresh operation or auto-refresh operation, and a second logic unit for performing a logic operation with respect to an output signal from the first logic unit and the second control signal to generate a third control signal having information about activation of the semiconductor device. The third control signal is enabled when at least one of the banks performs the self-refresh operation or auto-refresh operation even though it is in the active state. | 07-23-2009 |
| 20090278582 | Circuit for controlling pulse width of auto-refresh signal and circuit for generating internal row address for auto refress - A circuit for controlling a pulse width of a refresh signal is provided. The circuit includes a first pulse width controller for receiving a first refresh signal having a first enable period, and generating a second refresh signal having a second refresh signal, and a second pulse width controller for receiving the second refresh signal, and generating a third refresh signal having a third enable period. | 11-12-2009 |
Hyung Wook Park, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110253431 | Printed circuit substrate and method of manufacturing the same - Disclosed herein are a printed circuit substrate and a method of manufacturing the same. The printed circuit substrate includes an insulating layer, and a circuit layer that includes a circuit pattern disposed on the insulating layer and a barrier layer that is disposed to cover at least one surface of the circuit pattern and suppresses electrochemical migration from the circuit pattern, thereby making it possible to achieve high-density and secure reliability, and the method of manufacturing the same. | 10-20-2011 |