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Hyung-Seuk
Hyung-Seuk Kim, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100277997 | Semiconductor memory device - The semiconductor memory device includes a first memory cell connected between a first word line and a bit line. The semiconductor memory device may also include a second memory cell connected between a second word line and an inverted bit line. Additionally, the memory device may include a precharger configured to charge the bit line and the inverted bit line to a first voltage before a read operation, a first sense amplifier having a first transistor connected between to the bit line and a first node, the first transistor including a gate to which a signal of the inverted bit line is applied. The semiconductor memory device may have a second transistor connected between the inverted bit line and a second node, the second transistor including a gate to which a signal of the bit line is applied, and the first sense amplifier configured to amplify a voltage of the bit line or the inverted bit line to a second voltage based on to the second voltage applied to one of the first node and the second nodes during the read operation. The semiconductor memory device may also have a bias unit configured to generate a voltage difference between the first node and the second node, and a sense amplifier driver configured to apply the second voltage to one of the first and second nodes based on one of the first and second selected word lines during the read operation. | 11-04-2010 |
| 20110058435 | SEMICONDUCTOR MEMORY DEVICE COMPRISING SENSE AMPLIFIERS CONFIGURED TO STABLY AMPLIFY DATA - A semiconductor memory device adjusts a timing interval between the activation of first and second amplifiers in a sense amplifier circuit based on the distance between the sense amplifier circuit and corresponding power supply. | 03-10-2011 |
Hyung-Seuk Kim, Hwaseong-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090268535 | SEMICONDUCTOR DEVICE GUARANTEEING STABLE OPERATION - A semiconductor device includes a data line pair formed of a data line and a complementary data line; a first sensing amplification unit including a first sensing amplifier and a second sensing amplifier that are cross-coupled with the data line and the complementary data line; a first variable current source supplying or flowing out a first variable current to the first sensing amplifier; and a second variable current source supplying or flowing out a second variable current to the second sensing amplifier. A current amount of the first variable current is different from a current amount of the second variable current. | 10-29-2009 |
| 20100074041 | SEMICONDUCTOR DEVICE INCLUDING ASYMMETRIC SENSE AMPLIFIER - A semiconductor device includes an alternating arrangement of memory cell blocks and sense amplifier blocks, such that the sense amplifier blocks include an interior sense amplifier block and a periphery amplifier block. The peripheral amplifier block includes a first sense amplification unit having a first sense amplifier and a second sense amplifier cross-coupled between a bit line and a complementary bit line. The first sense amplifier supplies/receives current to/from the bit line, the second sense amplifier provides/receives current to/from the complementary bit line, and a current driving capability for the first sense amplifier is greater than a current driving capability of the second sense amplifier. | 03-25-2010 |
| 20100141329 | Temperature sensor and method of compensating for change in output characteristic due to varying temperature - Described is a method and apparatus for compensating for a change in an output characteristic of a temperature sensor due to varying temperature. The temperature sensor includes a temperature sensing core, an analog-to-digital converter, a counter, and a temperature compensating circuit. The temperature sensing core generates a sense voltage corresponding to a sensed temperature. The analog-to-digital converter converts the sense voltage into a digital signal and generates a conversion signal. The temperature compensating circuit generates a counter clock signal that varies according to a temperature change. The counter counts the number of pulses of the counter clock signal according to the conversion signal. | 06-10-2010 |
Hyung-Seuk Kim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080284501 | REFERENCE BIAS CIRCUIT FOR COMPENSATING FOR PROCESS VARIATION - A reference bias circuit is provided. The reference bias circuit includes a voltage detector, an operational amplifier, a compensation circuit, and a reference current generator. The voltage detector detects a first input voltage and a second input voltage of the operational amplifier based on a voltage of a first node and a voltage of a second node. The voltage of the first and second nodes varies with temperature, which changes the first input voltage and the second input voltage and thus changes the output voltage of the operational amplifier. The compensation circuit compensates for the variation of the voltage of the first and second nodes caused by temperature and/or process variation, thereby preventing the variation of a reference current generated by the reference current generator based on the output voltage of the operational amplifier. | 11-20-2008 |
| 20090102533 | Temperature Independent Delay Circuits - Delay circuits are provided. Some embodiments of delay circuits herein include a delay line including multiple delay cells connected in series and a variable voltage supplier operative to output a voltage value proportional and/or inversely proportional to a temperature. Delay circuits may include at least one loading capacitor that includes a first end that is connected to an output port of the delay cell and a second end that is connected to an output port of the variable voltage supplier., the at least one loading capacitor including a capacitance that is decreased corresponding to an increase in temperature when a positive voltage is applied across the first end and the second end of the at least one loading capacitor. | 04-23-2009 |