Patent application number | Description | Published |
20120140584 | SEMICONDUCTOR SYSTEM, SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR INPUT/OUTPUT OF DATA USING THE SAME - A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller. | 06-07-2012 |
20120273961 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a plurality of semiconductor chips which are stacked; and an auxiliary semiconductor chip configured to recover and transmit signals of the plurality of semiconductor chips through a plurality of through vias which extend vertically, at a predetermined time interval. | 11-01-2012 |
20130031439 | SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM HAVING THE SAME - A semiconductor memory apparatus includes: a memory cell area including a plurality of memory cell arrays stacked therein, each memory cell array having a plurality of memory cells integrated and formed therein to store data and a plurality of through-lines formed therein to transmit signals; and a control logic area configured to generate parity bits using a data signal inputted to the memory cell area and transmit the generated parity bits and the data signal to different through-lines. | 01-31-2013 |
20130092936 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal. | 04-18-2013 |
20130326162 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a controller configured to control a first memory device to process a request for the first memory device and a second memory device. The controller receives the request for the first memory device, determines a data damage risk of cells connected to a second signal line adjacent to a first signal line of the first memory device corresponding to a requested address by referring to information indicating a data damage risk, and stores data of the cells connected to the second signal line in the second memory device when determining that there is a data damage risk. | 12-05-2013 |
20140006863 | TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME | 01-02-2014 |
20140006901 | MEMORY SYSTEM | 01-02-2014 |
20140006902 | SEMICONDUCTOR DEVICE INCLUDING ECC CIRCUIT | 01-02-2014 |
20140092693 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device may test a semiconductor memory device by storing a data sample that is sampled from among data requested to be written into a semiconductor memory device and by comparing the data sample with data read from the semiconductor memory device which corresponds to the data sample. | 04-03-2014 |
20140177358 | ADDRESS COUNTING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A semiconductor apparatus includes a first memory die; a second memory die; and a processor configured to provide an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and provide an external command, an external start address and an external end address, which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be transferred to and stored in the second memory die. | 06-26-2014 |
20140181439 | Memory system - A memory system includes a processor, one or more volatile memory dies stacked with the processor and one or more nonvolatile memory dies stacked with the processor and the volatile memory dies. The processor transfers data stored in the volatile memory die to the nonvolatile memory die in response to a backup signal, and transfers the data stored in the nonvolatile memory die to the volatile memory die in response to a recovery signal. | 06-26-2014 |
20140181449 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - A memory system includes a memory unit and a memory controller. The memory unit includes a plurality of memory banks, wherein an information stored in a memory bank is accessed via a word line and a bit line. The memory controller is configured to limit repetitive accessing of a same word line or a same bit line so that the number of consecutive access is less than a predetermined critical value. | 06-26-2014 |