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Hyunchul
Hyunchul Cho, Ulsan KR
| Patent application number | Description | Published |
|---|---|---|
| 20110102145 | REMOTE CONTROL APPARATUS WITH DIALING SCHEME PROVIDING HAPTIC SENSATIONS - A remote control apparatus that provides haptic sensations. The remote control apparatus includes a dial, a motor, a rotary encoder, an encoder counter, a control unit and a motor controller. The remote control apparatus further includes a storage unit, a movement detection unit and a display unit. When a user selects an icon displayed on the display unit by rotating the dial, the control unit interprets the user instruction through the rotary encoder and the encoder counter to control the motor to generate torque for causing a haptic sensation corresponding to the interpreted instruction via the motor controller. While the haptic sensation is conveyed to the user through the dial, the control unit controls an appliance to perform the interpreted instruction thereon. | 05-05-2011 |
Hyunchul Jeong, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20110099622 | APPARATUS FOR DETECTING AND FILTERING APPLICATION LAYER DDOS ATTACK OF WEB SERVICE - Disclosed is a DDoS attack detection and response apparatus. The DDoS attack detection and response apparatus comprises: a receiver unit receiving HTTP requests from a client terminal which is characterized as an IP address; a data measuring unit computing the number of HTTP requests by IP and the number of URIs per HTTP over a certain time period; a DDoS discrimination unit comparing the number of HTTPs per URI with a threshold value and defining an access of the client terminal having the IP address as a DDoS attack when the number of HTTPs per URI is larger than the threshold value; and a blocking unit blocking packets from the IP address when the DDoS discrimination unit detects a DDoS attack. | 04-28-2011 |
| 20110107412 | APPARATUS FOR DETECTING AND FILTERING DDOS ATTACK BASED ON REQUEST URI TYPE - Provided is an apparatus for detecting and responding to a DDoS attack. The apparatus includes: a receiver unit configured to receive an HTTP request from a client terminal having a predetermined IP address; a data measuring unit configured to compute a number of a pre-defined URI in the received HTTP request by IP for a predetermined measuring time period; a DDoS discrimination unit configured to compare the computed number of the pre-defined URI with a pre-defined threshold and configured to detect an access of the client terminal with the IP address as the DDoS attack when the number of the pre-defined URI is greater than the threshold; and a blocking unit configured to block the access of the client terminal when the DDoS discrimination unit detects the DDoS attack. | 05-05-2011 |
Hyunchul Jung, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20120115019 | ENERGY STORAGE MODULE - Provided is an energy storage module including a cell structure having at least one energy storage cell and a package structure which covers the cell structure to package the cell structure, wherein the package structure includes a metal foil and a protective coating layer which covers the metal foil and is made of at least one of a silicon-based material and a fluorine-based material. | 05-10-2012 |
Hyunchul Kang, Ichon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090243090 | MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS - A mock bump system includes providing a flip chip integrated circuit having an edge and forming a mock bump near the edge. | 10-01-2009 |
Hyunchul Kim, Kyungbuk KR
| Patent application number | Description | Published |
|---|---|---|
| 20100156885 | LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME - A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line connecting a last source drive IC of the N source drive ICs to the timing controller. A swing width of an output voltage of the timing controller increases in proportion to a distance between the timing controller and the N source drive ICs. | 06-24-2010 |
| 20100277494 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DRIVING THE SAME - A liquid crystal display device and a method of driving the same are disclosed. The liquid crystal display device includes a liquid crystal display panel including data lines, gate lines crossing the data lines, and liquid crystal cells arranged in a matrix format at each of crossings of the data lines and the gate lines; a data drive circuit that converts digital video data into a positive/negative data voltage using gamma reference voltages to supply the positive/negative data voltage to the data lines; and a gamma voltage adjusting unit that increases a potential of each of the gamma reference voltages during a blanking period when a polarity of the positive/negative data voltage is inverted. | 11-04-2010 |
Hyunchul Kim, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20120037970 | MICROELECTRONIC MEMORY DEVICES HAVING FLAT STOPPER LAYERS AND METHODS OF FABRICATING THE SAME - Memory devices comprise a microelectronic substrate including a cell array region and a peripheral region adjacent the cell array region, the cell array region including therein an array of memory cells and the peripheral region including therein peripheral circuits for the array of memory cells, the microelectronic substrate including a lower layer that extends across the cell array region and across the peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, the insulating layer extending across the cell array region and the peripheral region and also including a flat outer surface from the cell array region to the peripheral region. A flat stopper layer is provided on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region. Finally, an array of memory cell capacitor storage nodes is provided in the cell array region that extend beyond the flat stopper layer and that penetrate through the flat stopper layer and the insulating layer. Related methods are also provided. | 02-16-2012 |