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Hyun, Yongin-Si
Dae-Eun Hyun, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120066075 | DISPLAY APPARATUS AND COMMERCIAL DISPLAY METHOD OF THE SAME - A display apparatus and a commercial display method of the same are provided. The display apparatus includes a display unit which displays at least one commercial image on a certain area; and a commercial executing unit which executes a function related to a selected commercial image if a selection signal for selecting one among the commercial images is received. | 03-15-2012 |
Deoc Hwan Hyun, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100294357 | Solar Cell and Method for Manufacturing the Same - A solar cell capable of improving efficiency, and a method for manufacturing the same is disclosed, wherein the method for manufacturing the solar cell comprises forming seeds in a predetermined surface portion of a semiconductor substrate doped with a first dopant through the use of silicon source gas; forming an irregularity structure on the semiconductor substrate by growing the seeds through a heat-treatment process; forming a first semiconductor layer doped with a second dopant in the semiconductor substrate with the irregularity structure, wherein the second dopant is different from the first dopant; and forming a front electrode at one side of the semiconductor substrate, the front electrode electrically connected to the first semiconductor layer. | 11-25-2010 |
Hyae Jung Hyun, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100255503 | MARKERS FOR DIAGNOSIS OF CANCER AND ITS USE - Disclosed herein are diagnostic markers CTHRC1, CANP and KIAA0101, which are overexpressed specifically in breast or colorectal cancer. A method for diagnosing the cancer by detecting the markers, and a method for preventing or treating by inhibiting the expression and activity of the markers are also disclosed. | 10-07-2010 |
Hyae Jung Hyun, Yongin-Si JP
| Patent application number | Description | Published |
|---|---|---|
| 20090209540 | Novel Biaryl Benzolmidazole Derivatives and Pharmaceutical Composition Comprising The Same - Disclosed are biaryl benzoimidazole derivatives. They have an inhibitory effect on calcium influx in HEK cells, thereby showing a powerful antagonistic effect on a vanilloid receptor, and further have an analgesic effect, thereby being useful for preventing or treating pain, acute pain, chronic pain, neuropathic pain, postoperative pain, migraine, arthralgia, neuropathies, nerve injury, diabetic neuropathy, neurological illness, neurodermatitis, stroke, bladder hypersensitivity, irritable bowel syndrome, a respiratory disorder such as cough, asthma, and chronic obstructive pulmonary disease, burning, psoriasis, itching, vomiting, irritation of the skin, eyes, and mucous membranes, gastric-duodenal ulcers, inflammatory intestinal diseases, and inflammatory diseases. | 08-20-2009 |
Jae-Woong Hyun, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090021988 | Nonvolatile memory device and method of operating fabricating the same - Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common source line. In the nonvolatile memory device, data may be erased from the memory transistors by applying an erasing voltage to the bit line or the common source line. | 01-22-2009 |
| 20100302870 | Nonvolatile memory device and method of operating and fabricating the same - Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common source line. In the nonvolatile memory device, data may be erased from the memory transistors by applying an erasing voltage to the bit line or the common source line. | 12-02-2010 |
Seokhun Hyun, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100213992 | Delay locked loop circuit and operation method thereof - A delay locked loop (DLL) circuit includes an analog DLL core and a digital DLL core. The analog DLL core receives an input clock signal of a first operating frequency. The digital DLL core receives an input clock signal of a second operating frequency equal to or lower than the first frequency. The analog and digital DLL cores operate selectively. The DLL core also includes a selection circuit configured to select one of the first and second DLL cores. The selection circuit may operate in response to a detection signal from a frequency detector which detects the frequency of the input clock signal. The selection circuit may also operate in response to a column address strobe writing latency signal that indicates frequency information of the input clock signal. | 08-26-2010 |
Seok-Hun Hyun, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100097111 | Semiconductor device including delay locked loop having periodically activated replica path - A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal. | 04-22-2010 |
| 20100156488 | DELAY-LOCKED LOOP CIRCUIT CONTROLLED BY COLUMN STROBE WRITE LATENCY - The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device. | 06-24-2010 |
Sungchae Hyun, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120121938 | WATERPROOF BATTERY PACK - A battery pack for an electric bicycle is disclosed. In one embodiment, the battery pack includes i) a lower case having a top, a bottom and an interior space formed between the top and bottom and ii) a battery cell placed in the interior space of the lower case, wherein the battery cell has first and second surfaces opposing each other, and wherein the first surface of the battery cell is closer to the bottom of the lower case than the second surface of the battery cell. The battery pack may further include i) a protection circuit board mounted on the second surface of the battery cell and placed in the interior space of the lower case, ii) an upper case formed over the top of the lower case and iii) a separator case formed between the protection circuit board and the upper case. | 05-17-2012 |
Sung-Hwan Hyun, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120124429 | APPARATUS AND METHOD FOR TRACING MEMORY ACCESS INFORMATION - An apparatus and method for tracing memory access information of a user program while ensuring a normal operation of the user program. An access permission about a memory region may be set to trace the memory access information. An instruction of the user program encounters a page fault according to the set access permission. If the page fault occurs, memory access information is stored based on the page fault, and apparatus executes an instruction causing the page fault while in a supervisor mode. | 05-17-2012 |