Patent application number | Description | Published |
20100243309 | Connecting structure for circuit board and connecting method using the same - Disclosed is a connection structure for a circuit board using a solder bump to arrange circuit boards. The circuit board connection structure includes a solder bump prepared on one of two circuit boards and a perforated part formed at the other of the circuit boards to receive the solder bump. Facing both circuit boards towards each other and inserting the solder bump into the perforated part, the circuit boards are desirably arranged. | 09-30-2010 |
20100248505 | Printed circuit board assembly and connecting method thereof - Disclosed herein is a printed circuit board and a connecting method thereof. The connecting method of the circuit board assembly may include molding the printed circuit board assembly by applying a resin to the printed circuit board assembly, exposing ends of the electrode terminals of a connector mounted on a printed circuit board by partially removing the molded printed circuit board assembly, and connecting a connection member to the exposed ends of the electrode terminals of the connector. Therefore, even if the whole of the printed circuit board assembly is molded, the connection member may be freely connected to the connector of the printed circuit board assembly. | 09-30-2010 |
20120043116 | Interconnection Structure Of Interposer With Low CTE And Packaging Component Having The Same - Disclosed herein are printed circuit board assemblies made of a brittle material such as silicon, glass or ceramic and provided with a connector to electrically connect the same to an external connection member, and a method for molding the printed circuit board assembly wherein the printed circuit board assembly is molded by applying a polymer resin thereto to impart hardness to the printed circuit board assembly, and an electrode terminal to connect the same to the external connection member is exposed to the outside. Disclosed herein is also an interconnection structure of an interposer, the interconnection structure electrically connected to a main printed circuit board (PCB) through a solder joint is interposed between the interposer and the solder joint to prevent or reduce concentration of stress on the solder joint caused by differences in coefficients thermal expansion between the interposer and the main PCB. | 02-23-2012 |
20120045910 | MOLDING METHOD OF PRINTED CIRCUIT BOARD ASSEMBLY - Disclosed is a printed circuit board assembly PBA on which a connector for electrical connection to an external connection element is mounted. Such an assembly may be formed with a molding method of a PBA which includes applying a polymer resin to the PBA to mold the PBA in order to offer stiffness thereto. The foregoing method of molding the PBA according to the present disclosure is a molding method of a PBA including a PCB and a connector mounted on the PCB to electrically connect the same to an external connection element. The method includes combining the connector with a connector cover, applying a resin to the PBA combined with the connector cover to execute molding of the PBA, and separating the connector cover from the molded PBA to expose the electrode terminal for an external connection element. | 02-23-2012 |
20150021082 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME - A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; first and second internal electrodes disposed in the ceramic body, the first internal electrode having first and second lead portions exposed to a first surface of the ceramic body in a width direction, and the second internal electrode having a third lead portion exposed to the first surface of the ceramic body in the width direction; first to third external electrodes disposed on the first surface of the ceramic body in the width direction to be connected to the first to third lead portions, respectively; and an insulation layer disposed on the first surface of the ceramic body in the width direction. Each of the first and second lead portions may be spaced apart from the third lead portion by a predetermined distance. | 01-22-2015 |
20150114705 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME - There are provided a multilayer ceramic capacitor and a board having the same. The multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from each other and connected to lead portions of internal electrodes, wherein an interval between adjacent lead portions is 500.7 μm or less, widths of one-side margin portions of the external electrodes in a length direction of the ceramic body that are not in contact with the corresponding lead portions are 20.2 μm or more. | 04-30-2015 |
20150124370 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor may include a ceramic body having a plurality of dielectric layers; first and second internal electrodes disposed in the ceramic body to be alternately exposed to the first and second end surfaces of the ceramic body, having the dielectric layers interposed therebetween; and first and second external electrodes electrically connected to the first and second internal electrodes, respectively. The first and second external electrodes may include: first and second internal conductive layers; first and second insulating layers; and first and second external conductive layers. | 05-07-2015 |
20150243438 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME - A multilayer ceramic capacitor and a board having the same are provided. The multilayer ceramic capacitor includes three external electrodes including a conductive layer, a nickel plating layer, and a tin plating layer sequentially stacked on a mounting surface of the ceramic body, and spaced apart from each other. When an outermost portion of a lead-out portion of an internal electrode exposed to the mounting surface is P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is b | 08-27-2015 |