Patent application number | Description | Published |
20080247243 | Semiconductor memory device including post package repair control circuit and post package repair method - Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank. | 10-09-2008 |
20090044063 | Semiconductor memory device and test system of a semiconductor memory device - A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle. | 02-12-2009 |
20090079496 | MULTI-CHIP PACKAGE FOR REDUCING PARASITIC LOAD OF PIN - Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods. | 03-26-2009 |
20110043235 | SEMICONDUCTOR DEVICE HAVING A PLURALITY OF PADS - A semiconductor device includes a plurality of sensor pads configured to receive a probe signal from a testing apparatus, and a plurality of normal pads configured to receive a driving signal to drive the semiconductor device. In the plurality of sensor pads and the plurality of normal pads, a length in a direction corresponding to one of progress directions of a plurality of needles of the testing apparatus is longer than a length in another progress direction of the plurality of needles. | 02-24-2011 |
20120257461 | METHOD OF TESTING A SEMICONDUCTOR MEMORY DEVICE - A method of testing a semiconductor memory device includes writing first data to a memory cell array in the semiconductor memory device, loading second data from the memory cell array onto a plurality of data pads of the semiconductor memory device, rewriting the second data to the memory cell array, and outputting test result data through one or more test pads. The first data is received from an external device through the one or more test pads, which correspond to one or more of the plurality of data pads. The test result data is based on the rewritten data in the memory cell array. | 10-11-2012 |
Patent application number | Description | Published |
20130164674 | NOVEL ACRYL MONOMER, POLYMER AND RESIST COMPOSITION COMPRISING SAME - Disclosed are an acrylic monomer having a structure represented by formula (1), a polymer containing a repeating unit derived from the acrylic monomer, and a resist composition prepared by using the polymer, which exhibits excellent adhesiveness, storage stability, and enhanced line width roughness, exhibits excellent resolution in both C/H patterns and L/S patterns, has an excellent process window so that an excellent pattern profile can be obtained regardless of the type of the substrate, and exhibits improved contrast. | 06-27-2013 |
20130171560 | ADDITIVE FOR RESIST AND RESIST COMPOSITION COMPRISING SAME - Provided are an additive for resist represented by the following formula (1), and a resist composition containing the additive. The additive according to the present invention can suppress leaching caused by water during an immersion lithographic process by increasing hydrophobicity of the surface of the resist film in the exposure at the time of applying the additive to a resist composition, and can form a fine resist pattern having excellent sensitivity and resolution at the time of applying the additive to a resist composition. | 07-04-2013 |
20130171561 | ADDITIVE FOR RESIST AND RESIST COMPOSITION COMPRISING SAME - A resist additive represented by Formula 1 below and a resist composition including the additive are disclosed. The resist additive improves hydrophobicity of the surface of the resist film to prevent materials from being leached in water during exposure of immersion lithography and is converted to have hydrophilicity by deprotection reaction during development. As a result, a micropattern of a resist film with excellent sensitivity and high resolution is formed. | 07-04-2013 |