| Patent application number | Description | Published |
|---|
| 20080285978 | OPTICAL HYBRID MODULE - Provided is an optical hybrid module in which an optical device, a filter, an amplifier and an antenna are hybrid-integrated, which includes: a silicon optical bench disposed on a substrate and having an optical fiber and an optical device; an amplifier disposed on the substrate and connected to the optical device disposed on the silicon optical bench to amplify a signal transmitted from the optical device; and an antenna disposed on the substrate to be connected to the amplifier and transmitting a signal amplified by the amplifier. Thus, a foot-print module may be embodied by disposing an antenna and a filter on a single- or multi-layer substrate and providing a bias required for the optical device and the amplifier through a solder ball. Also, due to the antenna and filter disposed on the substrate, an expensive connector is not needed, and thus a production costs can be reduced. | 11-20-2008 |
| 20090134944 | CAPACITIVE-DEGENERATION DOUBLE CROSS-COUPLED VOLTAGE-CONTROLLED OSCILLATOR - A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance. | 05-28-2009 |
| 20090146184 | SEMICONDUCTOR DEVICE WITH T-GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance. | 06-11-2009 |
| 20090146197 | PHOTO-DETECTOR ARRAY DEVICE WITH ROIC MONOLITHICALLY INTEGRATED FOR LASER-RADAR IMAGE SIGNAL AND MANUFACTURING METHOD THEREOF - A photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal and a manufacturing method thereof are provided. According to the photo-detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate, so that it is possible to simplify manufacturing processes and to greatly increasing yield. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically speared from each other by using a polyimide. Therefore, a PN junction surface of the photodiode is buried, so that a surface leakage current can be reduced and an electrical reliability can be improved. In addition, a structure of the control devices can be simplified, so that image signal reception characteristics can be improved. | 06-11-2009 |
| 20090146724 | SWITCHING CIRCUIT FOR MILLIMETER WAVEBAND CONTROL CIRCUIT - Provided is a switching circuit for a millimeter waveband control circuit. The switching circuit for a millimeter waveband control circuit includes a switching cell disposed on a signal port path to match an interested frequency and including at least one transistor coupled vertically to an input/output transmission line and a plurality of ground via holes disposed symmetrically in an upper portion and a lower portion of the input/output transmission line; capacitors for stabilizing a bias of the switching cell; and bias pads coupled in parallel to the capacitor to control the switching cell. Therefore, the switching circuit may be useful to improve its isolation by simplifying its design and layout through the use of symmetrical structure of optimized switching cells without the separate use of different switch elements, and also to reduce its manufacturing cost through the improved yield of the manufacturing process and the enhanced integration since it is possible to reduce a chip size of an integrated circuit in addition to its low insertion loss. | 06-11-2009 |
| 20090261481 | WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost. | 10-22-2009 |
| 20100090761 | PSK DEMODULATOR USING TIME-TO-DIGITAL CONVERTER - A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified. | 04-15-2010 |
| 20100134160 | FREQUENCY SYNTHESIZER - There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency. | 06-03-2010 |
| 20100134192 | FREQUENCY CALIBRATION LOOP CIRCUIT - A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting a oscillation frequency according to control value; a programmable divider dividing the oscillation frequency according to a division ratio; a counter counting the number of clocks of the divided frequency by using a reference frequency; and a frequency detector outputting a value obtained by subtracting the number of the counted clocks from a reference comparison value, a value obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider, as the control value of the oscillator. | 06-03-2010 |
| 20100134195 | CAPACITOR HAVING VARIABLE CAPACITANCE AND DIGITALLY CONTROLLED OSCILLATOR INCLUDING THE SAME - There is provided a capacitor having variable capacitance, which forms different capacitances according to a control signal by applying a switch to a metal-oxide-metal (MOM) structure plate capacitor using a CMOS process. The capacitor includes a stack structure including a plurality of metal layers including a first metal layer, and a plurality of dielectric layers respectively interposed between the plurality of metal layers, and a switch part including at least one switch having one side connected to at least one metal layer among the plurality of metal layers other than the first metal layer. The first metal layer and the other side of the switch serve as both terminals of the capacitor, and at least two capacitances are provided between both terminals of the capacitor upon controlling a short/open of the switch. | 06-03-2010 |
| 20100134334 | METHOD AND DEVICE FOR DIGITALLY CORRECTING DC OFFSET - There is provided a digital Direct Current (DC) offset correction method and device. The device includes a digital-analog converter charging a load capacitor according to an input code value and generating an initial voltage value of the load capacitor; a comparator comparing an output DC offset value of a discrete-time amplifier and filter on the basis of the initial voltage value with a preset output DC offset value when the discrete-time amplifier and filter and the load capacitor are connected to each other; and a controller changing the input code value of the digital-analog converter according to comparison result of the comparator. | 06-03-2010 |
| 20100134335 | APPARATUS FOR COMPENSATING FOR ERROR OF TIME-TO-DIGITAL CONVERTER - An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors. | 06-03-2010 |
| 20100135446 | DIGITAL-INTENSIVE RF RECEIVER - A digital-intensive RF receiver including: a first filter unit configured to allow an RF signal of a pre-set frequency band among RF signals to pass therethrough; a low noise amplifier (LNA) configured to amplify the RF signal from the first filter unit such that the RF signal has a pre-set magnitude; a second filter unit configured to allow an RF signal of a pre-set frequency band among RF signals from the LNA to pass therethrough; a clock generation unit configured to generate a pre-set reference frequency signal and generate a sub-sampling clock having a pre-set frequency lower than an RF carrier frequency by using the reference frequency signal; a sub-sampling A/D conversion unit configured to A/D-convert the RF signal from the second filter unit into a digital signal according to the sub-sampling clock from the clock generation unit, divide the RF signal into a plurality of frequency bands and sub-sample them during the A/D conversion process and perform noise shaping by the sub-channels included in the RF signal; and a digital processing unit configured to process a digital signal from the sub-sampling A/D conversion unit according to a system clock generated by using the reference frequency signal from the clock generation unit. | 06-03-2010 |
| 20100141315 | APPARATUS FOR LINEARIZATION OF DIGITALLY CONTROLLED OSCILLATOR - There is provided an apparatus for the linearization of a digitally controlled oscillator. The apparatus includes a first filter outputting only a low frequency band signal of an input signal to the digitally controlled oscillator; a negative feedback loop causing the signal of an input port of the digitally controlled oscillator to pass through a frequency table and a frequency-to-digital code mapper in sequence and correcting an input of the digitally controlled oscillator by performing negative feedback to an input port of the first filter; and a frequency table generator storing a frequency value of an output signal of the digitally controlled oscillator in the frequency table. | 06-10-2010 |
| 20100142648 | APPARATUS AND METHOD FOR I/Q MISMATCH CALIBRATION - There is provided an apparatus and method for In-phase/Quadrature-phase (I/Q) mismatch calibration. The apparatus includes: a symmetrical point extracting part receiving continuous wave signals and extracting an I/Q channel average locus of the continuous wave signals; an error extracting part extracting a degree of distortion of the continuous wave signals from the extracted I/Q channel average locus; and a calibrating part calibrating a mismatch between I-channel signals and Q-channel signals of the continuous wave signals using the degree of distortion of the continuous wave signals. | 06-10-2010 |
| 20100144281 | APPARATUS AND METHOD FOR REMOVING INTERFERENCE SIGNAL USING SELECTIVE FREQUENCY PHASE CONVERTER - An apparatus and method for removing an interference signal using a selective frequency phase converter are disclosed. The apparatus for removing an interference signal using a selective frequency phase converter includes: a first phase converter configured to convert a phase of a received RF signal to differentially output first and second signals having a phase difference of 180° from each other; a second phase converter configured to receive the first signal and selectively convert the phase of a particular frequency band; a third phase converter configured to receive the second signal and selectively convert the phase of a particular frequency band; a timing controller configured to correct a signal delay time between the output from the second phase converter and that of the third phase converter; and an adder configured to add an output from the second phase converter and an output from the third phase converter, wherein the second and third phase converters phase-convert the first and second signals such that the phases of the signals of the particular frequency bands do not have a phase difference of 180° from each other. | 06-10-2010 |
| 20100145482 | DIGITAL PROPORTIONAL INTEGRAL LOOP FILTER - A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value. | 06-10-2010 |
| 20100173443 | METHOD OF MANUFACTURING A PHOTO-DETECTOR ARRAY DEVICE WITH ROIC MONOLITHICALLY INTEGRATED FOR LASER-RADAR IMAGE SIGNAL - A method of manufacturing a photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal. A detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically separated from each other using a polyamide, whereby a PN junction surface of the photodiode is buried to reduce surface leakage current and improve electrical reliability, and the structure of the control devices can be simplified to improve image signal reception characteristics. | 07-08-2010 |
| 20100201457 | HYBRID BALUN APPARATUS - A hybrid balun apparatus are disclosed. The hybrid balun apparatus can support both the reception mode and the transmission mode and be advantageous for a high level of integration, by replacing two transformers disposed at a reception path and a transmission path with a single transformer and integrating a T/R switch and a balun into a one chip. Therefore, an IC according to integration extends to a front stage of an antenna to facilitate interfacing between elements, and a burden for designing at a rear stage (i.e., LNA in the reception mode, and PA in the transmission mode) can be reduced. | 08-12-2010 |
| 20100271072 | DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME - There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result. | 10-28-2010 |
| 20100322361 | DIGITAL RECEIVER - In a digital receiver, a noise attenuation and signal magnitude mapping variable amplifying unit includes a filter and an amplifier, amplifies and band-bass filters an analog signal and attenuating white noise and an interference signal other than a band signal. An ADC performs sub sampling on a carrier frequency of a desired signal and performs oversampling on the band of the desired signal by using a sampling frequency to convert the analog signal which has passed through the noise attenuation and signal magnitude mapping variable amplifying unit into a digital signal of a direct conversion frequency band or an intermediate frequency band. The ADC has a dynamic range for processing both the desired signal and an undesired signal adjacent to the desired signal. A digital signal processing unit converts a signal frequency of the digital signal or digital-filters an undesired signal within the digital signal and processes the digital signal by digitally adjusting a gain. | 12-23-2010 |
| 20110084865 | DIGITAL RF CONVERTER AND RF CONVERTING METHOD THEREOF - Provided are a digital radio frequency (RF) converter and an RF converting method thereof. The RF frequency converter includes first and second RF output terminals of a differential form outputting an RF signal; a differential switch selectively connecting first and second nodes into the first and second RF output terminals in response to an oscillating waveform; at least one digital delay device column outputting a plurality of unit bits by sequentially delaying an input bit corresponding to the digital input signal; a front-end processor summing an output of the at least one digital delay device column; a plurality of current sources; and a plurality of first switches corresponding to the plurality of current sources, respectively, and delivering currents of current sources whose number corresponds to the sum value of the front-end processor among the plurality of current sources, to one of the first and second nodes. | 04-14-2011 |
| 20110135045 | WIDEBAND RECEIVER - Provided is a wideband receiver that has a smaller area and consumes less power and can prevent harmonic mixing occurring due to an increase in the number of communications systems using wideband. A wideband receiver according to an aspect of the invention may include: an front-end unit receiving and performing low-pass filtering on a wideband input signal in a continuous-time domain; and a down-conversion unit sampling and holding an output signal of the front-end unit according to a local oscillator signal and performing low-pass filtering on the output signal in a discrete tie domain. | 06-09-2011 |
| 20110148490 | TIME-TO-DIGITAL CONVERTER AND ALL DIGITAL PHASE-LOCKED LOOP INCLUDING THE SAME - An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency. | 06-23-2011 |
| 20110148684 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER - There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code. | 06-23-2011 |
| 20110150125 | DIGITAL RF CONVERTER, DIGITAL RF MODULATOR AND TRANSMITTER INCLUDING THE SAME - There are provided a digital RF converter capable of improving a dynamic range and a signal to noise ratio of a transmitter and a digital RF modulator and a transmitter including the same. The digital RF converter may include: a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed; a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed; and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed. | 06-23-2011 |
| 20110150138 | HIGH LINEARITY MIXER AND DIRECT CONVERSION RECEIVER USING THE SAME - A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal. | 06-23-2011 |
