Hyun Jo
Hyun Jo Jun, Valparaiso, IN US
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20140147329 | HIGH SILICON BEARING DUAL PHASE STEELS WITH IMPROVED DUCTILITY - A dual phase steel (martensite+ferrite) having a tensile strength of at least 980 MPa, and a total elongation of at least 15%. The dual phase steel may have a total elongation of at least 18%. The dual phase steel may also have a tensile strength of at least 1180 MPa. The dual phase steel may include between 0.5-3.5 wt. % Si, and more preferably between 1.5-2.5 wt. % Si. | 05-29-2014 |
20140205488 | Ultra Fine-Grained Advanced High Strength Steel Sheet Having Superior Formability - A cold rolled, annealed TRIP steel sheet which has a composition including (in wt. %): C: 0.1-0.3; Mn: 4-10, Al: 0.05-5, Si: 0.05-5; and Nb: 0.008-0.1, the remainder being iron and inevitable residuals. The cold rolled sheet has an ultimate tensile strength of at least 1000 MPa, and a total elongation of at least 15%. The cold rolled sheet may have at least 20% retained austenite in its microstructure and may have greater than 50% lath-type annealed ferrite structure. The cold rolled sheet may have an ultra fine grain size of less than 5 micron for the retained austenite and ferrite. | 07-24-2014 |
Hyun Jo Yang, Chungcheongbuk-Do KR
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20090002672 | EXPOSURE APPARATUS HAVING THE SAME ID BIAS - An exposure apparatus includes an exposure light source generating light to be emitted to photomask, a projection lens for projecting the light having passed through the photomask to wafer, and a transmittance adjustment filter in projection lens the transmittance adjustment filter varies the transmittance of the light projected into the projection lens as a function of position in the projection lens. | 01-01-2009 |
20090246963 | Exposure Apparatus Applying Polarization Illuminator and Exposure Method Using the Same - An exposure apparatus for transferring patterns on a phase shift mask into a wafer according to the present invention comprises a light source, a polarized light illuminator that selectively passes through a TM mode polarized light of light from the light source to cause it to be incident onto the phase shift mask, a polarization mode translator that translates the TM mode polarized light passing through the phase shift mask into TE mode polarized light, and a lens system irradiating the TE mode polarized light from the polarization mode translator on the wafer. | 10-01-2009 |
Hyun Jo Yang, Cheongiu-Si KR
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20090110261 | Apparatus and Method for Verifying Pattern of Semiconductor Device - An apparatus and method for verifying the pattern of a semiconductor device provides for automatically detecting the leaning of pattern by using a design layout and the upper and the lower SEM (Scanning Electron Microscope) image of the pattern formed according to the design layout. | 04-30-2009 |
Hyun Jo Yang, Cheongju-Si KR
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20090007052 | Method for Verifying Pattern of Semiconductor Device - Provided is a method for verifying a pattern of a semiconductor device. In the method, a designed layout of target patterns is provided, and transferring the designed layout on a wafer to form wafer patterns. Wafer patterns image contour is obtain. The image contour for wafer patterns on the designed layout are matched, After edge differences between the designed layout and the wafer patterns image contour are extracted, a checking layout for detecting wafer pattern defects is obtain by adding the edge differences on the designed layout. Defects on the checking layout is identified to verify the patterns in view of processes before fabrication of a photomask. | 01-01-2009 |
20100279505 | METHOD FOR FABRICATING PATTERNS ON A WAFER THROUGH AN EXPOSURE PROCESS - A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First photoresist patterns are formed by performing a first exposure and development on the first photoresist layer. An etch process is performed using the first photoresist patterns and the fence as an etch mask. The fence is formed by selectively exposing a negative resist using a light shielding blade, and at this time, the first photoresist layer is formed including a positive resist. | 11-04-2010 |
20100316940 | Photomask for Forming Contact Hole in Semiconductor Device - Disclosed is a photomask for forming a contact hole arranged on a wafer in a zigzag form along a transverse direction, including: a light transmitting substrate; a main pattern disposed on the light transmitting substrate with a zigzag form as an upper main pattern disposed in a relatively upper portion and a lower main pattern disposed in a relatively lower portion are arranged alternately along a transverse direction; a first lower auxiliary pattern extending in a vertical direction and disposed adjacently to a lower portion of the upper main pattern; a first upper auxiliary pattern extending in a vertical direction and disposed adjacently to an upper portion of the lower main pattern; a second lower auxiliary pattern extending in the transverse direction and connecting the first lower auxiliary patterns with each other; and a second upper auxiliary pattern extending in the transverse direction and connecting the first upper auxiliary patterns with each other. | 12-16-2010 |
20120156850 | METHOD FOR FABRICATING FINE PATTERN - A method for fabricating a fine pattern includes forming a first photomask including first light transmission regions set in a line shape over a first phase shift mask (PSM) region and a first binary mask (BM) region adjacent to the first phase shift mask region. A second photomask may be formed to include second light transmission regions set in a line shape over a second phase shift mask region and a second binary mask region adjacent to the second phase shift mask region, wherein the second light transmission regions intersect the first light transmission regions. A resist layer may first be exposed using the first photomask and secondly exposed using the second photomask. The first and secondly exposed resist layer may be developed to form resist patterns with open regions corresponding to portions where the first light transmission regions intersect the second light transmission regions. | 06-21-2012 |
Hyun Jo Yang, Cheongju KR
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20130221531 | SEMICONDUCTOR DEVICE, MEMORY SYSTEM AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes first pads having centers offset in a first direction, wherein the first pads are arranged in a second direction crossing the first direction; second pads separated in the first direction from the first pads and arranged in the second direction, wherein centers of the second pads are offset in the first direction; first gate lines coupled to the first pads, respectively; and second gate lines coupled to the second pads, respectively. | 08-29-2013 |
Hyun-Jo Kim, Seoul KR
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20120207736 | COMPOSITION FOR CARTILAGINOUS TISSUE REPAIR AND A PRODUCTION METHOD THEREFOR - The present invention relates to a composition for cartilaginous tissue repair and to a production method therefor. The present invention comprises the steps of: (a) dissolving freeze-dried fibrinogen in an aprotinin solution; (b) dissolving freeze-dried thrombin in a stabilizing solution; (c) mixing an enriched collagen solution with thrombin and the stabilizing solution; and installing the fibrinogen solution (a) to one side of a dual kit and the solution (c) containing the collagen to the other side, and then mixing and injecting into damaged cartilaginous tissue. In the present invention, which is constituted as described above, biomaterials such as collagen and fibrin are mixed so as to allow damaged cartilaginous tissue to be repaired to a state allowing transplantation onto the tissue, and efficient regeneration is induced, thereby making it possible to reduce surgery-related stress on people and animals while inducing relatively rapid and efficient cartilage repair and regeneration. | 08-16-2012 |
20150054089 | SEMICONDUCTOR DEVICES HAVING 3D CHANNELS, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING 3D CHANNELS - A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film, and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film. | 02-26-2015 |
Hyun-Jo Kim, Gyeonggi-Do KR
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20090067216 | RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS - A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation. | 03-12-2009 |
20090135642 | RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS OPERATING RESPONSIVE TO READ OPERATIONS - A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block. | 05-28-2009 |
20110310657 | RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS OPERATING RESPONSIVE TO READ OPERATIONS - A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block. | 12-22-2011 |
Hyun-Jo Kim, Hwaseong-Si KR
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20100213558 | Magnetic Memory Device - A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions. | 08-26-2010 |