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Hyun Jo

Hyun Jo Yang, Cheongju-Si KR

Patent application numberDescriptionPublished
20090007052Method for Verifying Pattern of Semiconductor Device - Provided is a method for verifying a pattern of a semiconductor device. In the method, a designed layout of target patterns is provided, and transferring the designed layout on a wafer to form wafer patterns. Wafer patterns image contour is obtain. The image contour for wafer patterns on the designed layout are matched, After edge differences between the designed layout and the wafer patterns image contour are extracted, a checking layout for detecting wafer pattern defects is obtain by adding the edge differences on the designed layout. Defects on the checking layout is identified to verify the patterns in view of processes before fabrication of a photomask.01-01-2009
20100279505METHOD FOR FABRICATING PATTERNS ON A WAFER THROUGH AN EXPOSURE PROCESS - A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First photoresist patterns are formed by performing a first exposure and development on the first photoresist layer. An etch process is performed using the first photoresist patterns and the fence as an etch mask. The fence is formed by selectively exposing a negative resist using a light shielding blade, and at this time, the first photoresist layer is formed including a positive resist.11-04-2010
20100316940Photomask for Forming Contact Hole in Semiconductor Device - Disclosed is a photomask for forming a contact hole arranged on a wafer in a zigzag form along a transverse direction, including: a light transmitting substrate; a main pattern disposed on the light transmitting substrate with a zigzag form as an upper main pattern disposed in a relatively upper portion and a lower main pattern disposed in a relatively lower portion are arranged alternately along a transverse direction; a first lower auxiliary pattern extending in a vertical direction and disposed adjacently to a lower portion of the upper main pattern; a first upper auxiliary pattern extending in a vertical direction and disposed adjacently to an upper portion of the lower main pattern; a second lower auxiliary pattern extending in the transverse direction and connecting the first lower auxiliary patterns with each other; and a second upper auxiliary pattern extending in the transverse direction and connecting the first upper auxiliary patterns with each other.12-16-2010

Hyun Jo Yang, Chungcheongbuk-Do KR

Patent application numberDescriptionPublished
20090002672EXPOSURE APPARATUS HAVING THE SAME ID BIAS - An exposure apparatus includes an exposure light source generating light to be emitted to photomask, a projection lens for projecting the light having passed through the photomask to wafer, and a transmittance adjustment filter in projection lens the transmittance adjustment filter varies the transmittance of the light projected into the projection lens as a function of position in the projection lens.01-01-2009
20090246963Exposure Apparatus Applying Polarization Illuminator and Exposure Method Using the Same - An exposure apparatus for transferring patterns on a phase shift mask into a wafer according to the present invention comprises a light source, a polarized light illuminator that selectively passes through a TM mode polarized light of light from the light source to cause it to be incident onto the phase shift mask, a polarization mode translator that translates the TM mode polarized light passing through the phase shift mask into TE mode polarized light, and a lens system irradiating the TE mode polarized light from the polarization mode translator on the wafer.10-01-2009

Hyun Jo Yang, Cheongiu-Si KR

Patent application numberDescriptionPublished
20090110261Apparatus and Method for Verifying Pattern of Semiconductor Device - An apparatus and method for verifying the pattern of a semiconductor device provides for automatically detecting the leaning of pattern by using a design layout and the upper and the lower SEM (Scanning Electron Microscope) image of the pattern formed according to the design layout.04-30-2009