Patent application number | Description | Published |
20110076533 | SECONDARY BATTERY - A secondary battery in which a fixing tape is attached to an electrode assembly, a positive electrode tab, a negative electrode tab, and a cap plate without use of an insulating case to prevent the electrode assembly from vibrating. The secondary battery includes an electrode assembly including a positive electrode plate to which a positive electrode tab is coupled, a negative electrode plate to which a negative electrode tab is coupled, and a separator interposed between the positive electrode plate and the negative electrode plate, a can having an opened part on one side to accommodate the electrode assembly, a cap assembly sealing the opened part of the can, and a fixing tape continuously attached from the electrode assembly to a bottom surface of the cap assembly while being attached to the positive electrode tab and the negative electrode tab. | 03-31-2011 |
20110292729 | Method of Controlling Non-Volatile Memory Device - A method of controlling a non-volatile memory device includes comparing the number of banks that are in operating states with a threshold value. If the number of the banks is smaller than the threshold value, data stored in a standby bank is read. If there is no bank having data to be read, a standby bank is programmed. If the number of the banks is equal to or greater than the threshold value or if the reading or the programming is performed, it is determined whether there is a reading or programming command to be performed. If there is the reading or programming command to be performed, the process is repeated from the comparing step. The programming may include programming of a most significant bit (MSB) page or a least significant bit (LSB) page. | 12-01-2011 |
20120124276 | DATA STORAGE DEVICE, USER DEVICE AND DATA WRITE METHOD - Disclosed is an address mapping method for a data storage device using a hybrid mapping scheme. The address mapping method determines whether write data includes a defined super sequential block (SSB), and selects an address mapping mode for the write data in accordance with whether or not a SSB is present. | 05-17-2012 |
20120151294 | METHOD AND APPARATUS FOR CORRECTING ERRORS IN MEMORY DEVICE - A memory controller analyzes read data received from a memory device and first error correction code (ECC) data of the read data. A control unit generates a plurality of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than a number of error bits that can be corrected using the first ECC data. An ECC block generates the first ECC data and second ECC data by using substantially the same algorithm to correct errors in each of the sub-data. The control unit transmits each of the sub-data, the first ECC data and the second ECC data to the memory device. | 06-14-2012 |
20120216094 | Controller, A Method Of Operating The Controller And A Memory System - The present disclosure provides a controller which comprises a command generator configured to generate a command to non volatile memory, and buffer configured to receive a first data and a second data and configured to combine the first data and the second data, an ECC unit configured to perform the ECC decoding. And the first page data may include at least one error bit corresponding to an error location table and the second page data may include at least one original bit which can be replaced with the error bit. The buffer may replace the at least one error bit with the said at least one original bit. The error location table may save information of location for the repeated error bit. | 08-23-2012 |
20130080684 | ADAPTER HAVING HIGH SPEED STORAGE DEVICE - An adapter, providing a selective connection between a host and mass storage device, includes a high-speed storage device, a host interface and a device interface. The high-speed storage device is provided on a front surface of a printed circuit board (PCB), and includes multiple nonvolatile memory devices and a controller configured to control operations of the nonvolatile memory devices. The host interface is on a back surface of the PCB, and is configured to interface between the high-speed storage device and the host. The device interface is on the back surface of the PCB, and is configured to interface between the high-speed storage device and the mass storage device. | 03-28-2013 |
20130132650 | STORAGE DEVICE BASED ON A FLASH MEMORY AND USER DEVICE INCLUDING THE SAME - Disclosed is a storage device which includes a flash memory storing data; and a controller controlling the flash memory and performing an invalidation operation in response to a trim command of a host, wherein the controller configures a trim sector bitmap using trim information provided from the host at the invalidation operation and manage the trim sector bitmap by a region unit. | 05-23-2013 |
20130159607 | MEMORY SYSTEM AND A PROGRAMMING METHOD THEREOF - A method of programming a storage device includes determining, at a controller of the storage device, that a first program mode of a plurality of program modes is to be entered in response to first information, wherein the first information includes a parameter associated with temperature, power consumption or input/output workload, and changing, using the controller, a program ratio of a first programming and a second programming of the storage device in the first program mode. | 06-20-2013 |
20140304457 | NONVOLATILE STORAGE DEVICE AND METHOD OF STORING DATA THEREOF - A data storing method of a nonvolatile storage device that includes a plurality of nonvolatile memory devices electrically connected to a plurality of channels is provided. The data storing method includes allocating part of write data provided from a host to the nonvolatile memory devices to each channel; determining whether at least one channel among the channels is present that is connected to a nonvolatile memory device in a last page offset state; and when the at least one channel is determined to be present, scheduling erase commands on the plurality of channels, scheduling write commands on the plurality of channels with respect to the allocated write data, and executing the erase commands and the write commands on the plurality of channels. | 10-09-2014 |