| Patent application number | Description | Published |
|---|
| 20090170545 | COGNITIVE RADIO COMMUNICATION APPARATUS AND METHOD WHICH ADAPTABLY CONTROLS SENSING REFERENCE LEVEL - A cognitive radio communication apparatus and method which adaptably controls a sensing reference level based on a transmission power of a transmitter is provided. A cognitive radio communication apparatus includes a sensing reference level control unit to adaptably control a sensing reference level based on a transmission power of a secondary transmitter included in a secondary network, and a fast sensing unit to determine whether a signal received for a predetermined time period exists based on the controlled sensing reference level. | 07-02-2009 |
| 20090251954 | VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM - Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit. | 10-08-2009 |
| 20090298439 | COGNITIVE RADIO COMMUNICATION SYSTEM RECOGNIZING INTERFERENCE BASED ON KNOWN SIGNAL - A cognitive radio (CR) communication apparatus and method is provided. A cognitive radio (CR) communication apparatus includes a signal receiving unit which receives signals from a primary user of a primary system and a secondary transmitter of a secondary system, the received signals including an element associated with at least one known signal of the secondary transmitter, and a determination unit which determines whether a signal of the primary user exists from among the received signals based on the element associated with the at least one known signal. | 12-03-2009 |
| 20090304110 | COGNITIVE RADIO COMMUNICATION SYSTEM USING MULTIPLE INPUT MULTIPLE OUTPUT COMMUNICATION SCHEME - A cognitive radio communication system using a multiple input multiple output (MIMO) communication technology is provided. A cognitive radio base station includes a plurality of antennas, a group setting unit to set at least one sensing terminal group that includes at least one sensing terminal among a plurality of terminals, and a signal generator to generate a transmission signal to transmit the transmission signal using channels formed between the plurality antennas and the plurality of terminals, so that the at least one sensing terminal is accorded a sensing time. | 12-10-2009 |
| 20090313524 | LOW DENSITY PARITY CODE ENCODING DEVICE AND DECODING DEVICE AND ENCODING AND DECODING METHODS THEREOF - A low density parity code (LDPC) encoding and decoding devices and encoding and decoding methods thereof are provided. An LDPC encoding device includes an information obtaining unit which obtains status information of at least two frequency bands, a matrix generation unit which generates a parity check matrix based on the status information, the parity check matrix including sub matrices which correspond to the at least two frequency bands, and an encoder which generates data bits and parity bits using an LDPC with the generated parity check matrix. | 12-17-2009 |
| 20100027326 | Memory device, memory system having the same, and programming method of a memory cell - A method of writing multi-bit data to a semiconductor memory device with memory cells storing data defined by a threshold value, the method comprising, for each memory cell, writing a least significant bit, verifying completion of writing the least significant bit, verifying including comparing a written value to one of a low least significant bit verification value and a high least significant bit verification value, and writing a next significant bit upon completion of writing the least significant bit. | 02-04-2010 |
| 20100086010 | COGNITIVE RADIO COMMUNICATION DEVICE FOR PERFORMING SPECTRUM SENSING AND DATA COMMUNICATION - A cognitive radio communication device including at least two radio frequency chains is provided. In order to perform a feature detection, the cognitive radio frequency device may reduce or eliminate a quiet time where a data communication is suspended using the at least two RF chains. While one RF chain performs the feature detection, another RF chain may perform the data communication. | 04-08-2010 |
| 20100091789 | COGNITIVE RADIO COMMUNICATION TERMINAL AND METHOD FOR DETECTING COLLISION USING FEATURE DETECTION - A cognitive radio communication terminal including a transmission processing unit to divide data by a quiet time slot that is allocated at a first point in time of a collision detection period, to transmit at least one portion of the divided data to a reception side, and a sensing unit to determine whether at least one of a feature information and an energy of another terminal is detected in a channel with the reception side during the quiet time slot of the first point in time. Where neither the feature information nor the energy of the other terminal is detected based on a determination of the sensing unit, the transmission processing unit transmits the remaining divided data. | 04-15-2010 |
| 20100093360 | COGNITIVE RADIO COMMUNICATION METHOD USING DYNAMICALLY ALLOCATED COMMON CONTROL CHANNEL INFORMATION - A cognitive radio base station may transmit, for each channel, common control channel information to a plurality of cognitive radio terminals at different points in time, respectively. Accordingly, the cognitive radio base station may receive a channel allocation request from the plurality of cognitive radio terminals receiving the common control channel information and allocate a plurality of channels to the plurality of cognitive radio terminals, respectively, to perform communication. In response to another terminal existing in a corresponding channel, the cognitive radio base station may update the common control channel information and switch to another channel to transmit subsequent common control channel information at, for example, a closest point in time to thereby broadcast the updated common control channel information to the plurality of cognitive radio terminals using the switched channel. | 04-15-2010 |
| 20100124105 | VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM - Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit. | 05-20-2010 |
| 20100172172 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SAME, AND VOLTAGE SUPPLY METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device, a semiconductor system including the same, and a voltage supply method of the semiconductor device are provided. The semiconductor device includes at least two semiconductor memory devices and a voltage supply controller configured to selectively supply a voltage to each of the at least two semiconductor memory devices. | 07-08-2010 |
| 20100172174 | SEMICONDUCTOR DEVICE HAVING ARCHITECTURE FOR REDUCING AREA AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation. | 07-08-2010 |
| 20100202182 | MEMORY DEVICES, SYSTEMS AND METHODS USING MULTIPLE 1/N PAGE ARRAYS AND MULTIPLE WRITE/READ CIRCUITS - A memory device architecture includes N arrays respectively for storing a 1/N of a page and N write/read circuits, where N is a natural number, respectively for writing or reading a 1/N of the page to/from each of the N arrays. | 08-12-2010 |
| 20100208381 | Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices - A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal. | 08-19-2010 |
| 20100208504 | Identification of data positions in magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices - In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains. | 08-19-2010 |
| 20100214831 | Memory device, memory system having the same, and programming method of a memory cell - A memory device includes an array of resistance change memory cells divided into a first memory block including a first selected memory cell of a first plurality of memory cells and a second memory block including a second selected memory cell of a second plurality of memory cells, and sensing and writing circuitry configured to simultaneously activate a line connected with the first and second selected memory cells. The first and second selected memory cells may be written by iteratively applying a level-controlled write signal to memory cells not having a programmed state equal to the write data until a verify-read operation indicates respective programmed states for the first and second selected memory cells are equal to the write data. | 08-26-2010 |
| 20100214862 | Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same - A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage. | 08-26-2010 |
| 20100218073 | Resistive Memory Devices and Methods of Controlling Operations of the Same - To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc. | 08-26-2010 |
| 20100220513 | Bi-Directional Resistive Memory Devices and Related Memory Systems and Methods of Writing Data - A bi-directional resistive memory device includes a memory cell array including a plurality of memory cells and an input/output (I/O) circuit. The I/O circuit is configured to generate a first voltage having a positive polarity and a second voltage having a negative polarity, provide one of the first voltage and the second voltage to the memory cell array through a bitline responsive to a logic state of input data, and adjust magnitudes of the first and second voltage when data written in the memory cell array has an offset. Related memory systems and methods are also provided. | 09-02-2010 |
| 20100223532 | SYSTEMS, DEVICES AND METHODS USING REDUNDANT ERROR CORRECTION CODE BIT STORAGE - A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit. | 09-02-2010 |
| 20100226165 | RESISTIVE MEMORY DEVICES HAVING A STACKED STRUCTURE AND METHODS OF OPERATION THEREOF - A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode. | 09-09-2010 |
| 20100246234 | Stacked memory devices - A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers. | 09-30-2010 |
| 20100246246 | Memory device, memory system having the same, and programming method of a memory cell - A nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, may be programmed by writing a least significant bit for each multi-level memory cell of the plurality of memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, writing a next significant bit for each multi-level memory cell. | 09-30-2010 |
| 20100284209 | INTEGRATED CIRCUIT MEMORY SYSTEMS AND PROGRAM METHODS THEREOF INCLUDING A MAGNETIC TRACK MEMORY ARRAY USING MAGNETIC DOMAIN WALL MOVEMENT - Provided are nonvolatile memory devices and program methods thereof. an integrated circuit memory system includes a memory array comprising at least one magnetic track, each of the at least one magnetic track including a plurality of magnetic domains and at least one read/write unit coupled thereto, decoding circuitry coupled to the memory array that is operable to select at least one of the magnetic domains, a read/write controller coupled to the memory array that is operable to read data from at least one of the plurality of magnetic domains and to write data to at least one of the plurality of magnetic domains via the at least one read/write unit coupled to each of the at least one magnetic track, and a domain controller coupled to memory array that is operable to move data between the magnetic domains on each of the at least one magnetic track. | 11-11-2010 |
| 20100284216 | INFORMATION STORAGE DEVICES USING MAGNETIC DOMAIN WALL MOVEMENT AND METHODS OF OPERATING THE SAME - An information storage device includes a first portion comprising at first at least one magnetic track, each of the at least one magnetic track in the first portion including a first plurality of magnetic domains and being configured to store a first type of data therein and a second portion comprising a second at least one magnetic track, each of the at least one magnetic track in the second portion including a second plurality of magnetic domains and being configured to store a second type of data therein, the second type of data being related to the first type of data. | 11-11-2010 |
| 20100304682 | CLUSTERING METHOD AND COMMUNICATION DEVICE FOR COORDINATED MULTIPOINT TRANSMISSION - A communication system performing a coordinated multipoint transmission is provided. A mobile station may measure expected channel quality information when an interference of a serving base station does not exist. The serving base station may determine whether a neighbor base station and the serving base station are eligible to perform the coordinated multipoint transmission. The serving base station may determine whether the neighbor base station and the serving base station are eligible to perform the coordinated multipoint transmission using a criterion associated with an evaluation of an increase in a transmission rate of the mobile station. | 12-02-2010 |
| 20100309705 | Stacked memory devices - A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups. | 12-09-2010 |
| 20100330917 | COMMUNICATION SYSTEM FOR DISTRIBUTEDLY MANAGING INTERFERENCE USING FEEDBACK MESSAGE - A method of operating a target terminal being serviced by a serving base station is provided. In a downlink case, the target terminal being served by the serving base station may provide a feedback message to a neighboring base station. The feedback message may be used by the neighboring base station to verify channel information between the serving base station and the target terminal, and channel information between the neighboring base station and the target terminal. In an uplink case, the neighboring base station may provide the feedback message to the target terminal. The target terminal may transfer, to the serving base station, channel information between the neighboring base station and a particular terminal, and channel information between the neighboring base station and the target terminal that are verified based on the feedback message. The feedback message may be transferred using a common shared channel or a random access channel. | 12-30-2010 |
| 20110014924 | SYSTEM AND METHOD FOR COOPERATIVE INTER-CELL INTERFERENCE CONTROL - A system to cooperatively control inter-cell interference is provided. A first frequency allocated to a central area of a serving cell associated with a serving base station may be allocated to a central area of a neighboring cell associated with a neighboring base station. A second frequency allocated to an edge area of the serving cell may be allocated to an edge area of the neighboring cell. Where a terminal is located in the edge of the neighboring cell, scheduling information, channel information, and data may be exchanged between the terminal and the serving base station. | 01-20-2011 |
| 20110032911 | COGNITIVE RADIO COMMUNICATION APPARATUS AND RADIO ACCESS TECHNOLOGY SELECTION METHOD OF COGNITIVE RADIO COMMUNICATION APPARATUS - A Cognitive Radio (CR) communication apparatus is provided. The CR communication apparatus may include a determination unit to determine any one of a plurality of Radio Access Technologies (RATs) as a temporary control RAT, an estimation unit to estimate an available resource and a channel state of each common RAT using the temporary control RAT, and a selection unit to calculate an available capacity of each of the common RATs using the available resource and the channel state, and to select an optimum RAT from the common RATs based on the available capacity of each of the common RATs. The common RATs may be used by the CR communication apparatus and a receiving CR communication apparatus from among the plurality of RATs. | 02-10-2011 |
| 20110034171 | COMMUNICATION SYSTEM AND METHOD FOR SINGLE-POINT TRANSMISSION AND RECEPTION AND COORDINATED MULTI-POINT TRANSMISSION AND RECEPTION - A communication system and method for single-point transmission and reception and coordinated multi-point transmission and reception are provided. The system and method include determining information associated with a channel status of a target terminal. The system and method also include selecting, with respect to the target terminal, one of single-point transmission and reception and coordinated multi-point transmission and reception based on the information associated with the channel status of the target terminal. | 02-10-2011 |
| 20110070884 | METHOD FOR MULTI-POINT COOPERATION CONSIDERING DELAY IN WIRELESS COMMUNICATION SYSTEM - Provided is a method of a multi-node cooperation considering a delay in a wireless communication system. A frame format may perform scheduling so that uplink cooperation terminals having a similar delay attribute may be classified into an uplink cooperation zone, to thereby prevent interference between the uplink cooperation zone and a non-cooperation zone. An extended cyclic prefix may be applied according to a delay attribute occurring due to an application of the multi-node cooperation. A cooperation base station of an uplink and a downlink may be determined based on the extended cyclic prefix. | 03-24-2011 |
| 20110086655 | TUNNELING CONTROL METHOD AND APPARATUS FOR COORDINATED MULTI-POINT TRANSMISSION, AND METHOD FOR TRANSMITTING DATA - A tunneling control method and apparatus for a coordinated multi-point transmission, and a method of transmitting data, are provided. The tunneling control method and the data transmission method may minimize a time delay that occurs because of the coordinated multi-point transmission between base stations. | 04-14-2011 |
| 20110110285 | SYSTEM AND METHOD FOR TRANSMITTING DATA IN A MULTI-CELL NETWORK - A communication system and method that receives data from a terminal using a cooperative reception scheme, is provided. Each terminal may generate multi-cell transmission data used for overcoming transmission delay and transmit, to each base station, a data frame including the multi-cell transmission data. | 05-12-2011 |
| 20110128939 | HIERARCHICAL-CELL COMMUNICATION SYSTEM USING ASYMMETRIC FEEDBACK SCHEME BASED ON CLASS OF ACCESS NETWORK - A small cell communication system may reduce interference occurring in a macro terminal through beamforming, even when using the same frequency resources as used by a macro communication system. For example, the small cell communication system may use a larger amount of radio resources than the macro communication system for transmission of feedback information in an uplink. For example, the small cell communication system may use a codebook having a larger size than a size of a codebook used by the macro communication system. | 06-02-2011 |
| 20110159897 | SYSTEM AND METHOD USING RATE SPLIT SCHEME BASED ON COOPERATION BETWEEN RECEIVERS - Each of a first transmitter and a second transmitter uses a rate split scheme. Each of the first transmitter and the second transmitter may transmit at least four sub-messages, and different transmission powers may be allocated to the at least four sub-messages. Also, each of receivers may cooperate with each other, may share sub-messages that act as interferences, and may extract desired messages using the shared sub-messages. | 06-30-2011 |
