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Hyun, Gyeonggi-Do
Dong Gyu Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100262003 | Separable Biopsy Device Integrated-Type Ultrasonic Diagnostic Apparatus - A separable biopsy device integrated-type ultrasonic diagnostic apparatus is disclosed. The separable biopsy device integrated-type ultrasonic diagnostic apparatus includes an ultrasonic diagnostic apparatus exposing one side of a diagnosis target and examining the diagnosis target at the other side of the diagnosis target, and a biopsy device located at the exposed side of the diagnosis target and detachably coupled to the ultrasonic diagnostic apparatus. The apparatus can perform ultrasound diagnosis and biopsy together, thereby providing the convenience of allowing the ultrasound diagnosis and the biopsy to be performed with a single apparatus, and can perform a biopsy based on ultrasound images obtained using the ultrasonic diagnostic apparatus without changing a position of a diagnosis target, enabling precise determination as to a position to be biopsied, that is, a target position into which the needle of the biopsy device will be inserted. | 10-14-2010 |
| 20100262004 | Biopsy Device and Ultrasonic Diagnostic Apparatus Including the Same - A biopsy device and a biopsy device integrated-type ultrasonic diagnostic apparatus are disclosed. The biopsy device includes a needle collecting a sample tissue from a diagnosis target, a needle guide guiding a movement path of the needle, and a biopsy kit with the needle guide movably disposed therein in a direction in which the needle is inserted into the diagnosis target. The biopsy device compressively supports a local point of the diagnosis target into which the needle will be inserted for biopsy, so that the shape of the diagnosis target is prevented from being changed upon insertion of the needle, thereby enhancing precision of biopsy diagnosis results while reducing examinee discomfort and inconvenience. | 10-14-2010 |
| 20100262011 | Ultrasonic Diagnostic Apparatus - An ultrasonic diagnostic apparatus is disclosed. The ultrasonic diagnostic apparatus includes a housing exposing one side of a diagnosis target while supporting the diagnosis target so as to maintain a shape of the diagnosis target, an oblique part obliquely formed on the housing to support the diagnosis target, and a probe unit disposed inside the housing to examine the diagnosis target. The ultrasonic diagnostic apparatus ensures efficient diagnosis of the overall diagnosis target without excessive compression of the diagnosis target causing examinee discomfort, and can support the diagnosis target so as to maintain the shape of the diagnosis target, thereby ensuring the provision of a constant quality of ultrasonic images upon repetitious diagnosis of the diagnosis target while improving reproducibility of diagnosis results. | 10-14-2010 |
Dong-Ho Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090309628 | SEMICONDUCTOR MEMORY DEVICE AND ON-DIE TERMINATION CIRCUIT - An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a termination resistance in response to the ODT drive signals of a corresponding drive signal generator. The drive signal generators are configured to supply the ODT drive signals to the ODT drive units to output a plurality of ODT control signals through the terminals in a test mode. | 12-17-2009 |
Hyae Jung Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090018124 | Novel Benzoimidazole Derivatives and Pharmaceutical Composition Comprising the Same - Disclosed herein are novel benzoimidazole derivatives functioning as antagonists to vanilloid receptor-1, and a pharmaceutical composition comprising the same. They are useful in preventing or treating pain, acute pain, chronic pain, neuropathic pain, postoperative pain, migraines, arthralgia, neuropathy, nerve injury, diabetic neuropathy, neurological illness, neurodermatitis, strokes, bladder hypersensitivity, irritable bowel syndrome, respiratory disorders such as asthma, chronic obstructive pulmonary disease, etc., burns, psoriasis, itching, vomiting, irritation of the skin, eyes, and mucous membranes, gastric-duodenal ulcers, inflammatory intestinal diseases, and inflammatory diseases. | 01-15-2009 |
| 20090028863 | MARKERS FOR DIAGNOSIS OF CANCER AND ITS USE - Disclosed herein are diagnostic markers CTHRC1, CANP and KIAA0101, which are overexpressed specifically in breast or colorectal cancer. A method for diagnosing the cancer by-detecting the markers, and a method for preventing or treating by inhibiting the expression and activity of the markers are also disclosed. | 01-29-2009 |
Hye Rin Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20120013832 | LIQUID CRYSTAL DISPLAY DEVICE - Disclosed is an LCD device which facilitates to realize a high aesthetic sense by obtaining a colorful and entirely-unified color screen under the circumstance that an image is not displayed in a turning-off state, wherein the LCD device comprises: a liquid crystal module which comprises a liquid crystal panel for displaying an image; a set cover which supports the liquid crystal module; and a color realization film which selectively transmits light with a predetermined wavelength when the liquid crystal module is turned-off, wherein the color realization film comprises a cholesteric liquid crystal layer (CLC), a quarter wave plate (QWP), and a first adhesive layer formed between the cholesteric liquid crystal layer (CLC) and the quarter wave plate (QWP). | 01-19-2012 |
Ji Young Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100155990 | METHOD FOR MANUFACTURING KEYPAD OF PORTABLE TERMINAL - Disclosed is a method for manufacturing a keypad of a portable terminal, in which a metal thin layer ( | 06-24-2010 |
Jung Ho Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090148896 | Hyperthermophilic DNA Polymerase and Methods of Preparation Thereof - The present invention relates to a hyperthermophilic DNA polymerase and a preparation method thereof. The invention provides a novel hyperthermophilic DNA polymerase isolated from a | 06-11-2009 |
Moon Pil Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20120133555 | METHOD AND SYSTEM FOR BUILDING LOCATION INFORMATION DATABASE OF ACCESS POINTS AND METHOD FOR PROVIDING LOCATION INFORMATION USING THE SAME - A method and system for building a database (DB) of location information of APs and providing AP location information in a shadow area of Global Positioning System (GPS) using the DB includes acquiring a reference location during a location information acquisition mode; collecting AP information of at least one AP by a mobile terminal by scanning periodically; calculating AP scan location where AP scan is executed; calculating AP location of the at least one AP using the AP information and the AP scan location; and building the AP location information DB by listing a mapping of the AP location to AP information. | 05-31-2012 |
Moon Un Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100072598 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip. | 03-25-2010 |
Myung Hwa Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100117325 | BRACKET FOR MOUNTING SHOCK ABSORBER - A bracket is provided to mount a shock absorber to a vehicle body. The bracket is configured to couple a distal end of a piston rod of the shock absorber to a vehicle body. The bracket is molded of a plastic material and includes a body having a recess formed thereon, the recess allowing a bush assembly to be inserted therein, and a flange extending from the body. The bracket is molded integrally with a metal insert. | 05-13-2010 |
Sangjin Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100099245 | Methods of Forming Semiconductor Devices - Provided are a semiconductor device and a method of forming the same. The method may include forming a metal oxide layer on a substrate and forming a sacrificial oxide layer on the metal oxide layer. An annealing process is performed on the substrate. A formation-free energy of the sacrificial oxide layer is greater than a formation-free energy of the metal oxide layer at a process temperature of the annealing process. | 04-22-2010 |
| 20100099269 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product. | 04-22-2010 |
| 20100102399 | Methods of Forming Field Effect Transistors and Devices Formed Thereby - Methods of forming field effect transistors include forming a first gate electrode on a semiconductor substrate and forming insulating spacers on sidewalls of the first gate electrode. At least a portion of the first gate electrode is then removed from between the insulating spacers to thereby expose inner sidewalls of the insulating spacers. Threshold-voltage adjusting impurities are then implanted into the semiconductor substrate, using the insulating spacers as an implant mask. These threshold-voltage adjusting impurities are selected from a group consisting of alkali metals from Group 1 of the periodic chart and halogens from Group 17 of the periodic chart. A second gate electrode is then formed between the inner sidewalls of the insulating spacers. | 04-29-2010 |
| 20120012942 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product. | 01-19-2012 |
Sang-Jin Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080305620 | METHODS OF FORMING DEVICES INCLUDING DIFFERENT GATE INSULATING LAYERS ON PMOS/NMOS REGIONS - Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer. | 12-11-2008 |
| 20100124805 | METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING GATES WITH DIFFERENT WORK FUNCTIONS USING NITRIDATION - A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer. A first gate and a second gate having different work functions are respectively formed in the first region and the second region by etching the gate electrode layer and the gate insulating layer | 05-20-2010 |
Soon-Young Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090053857 | SEMICONDUCTOR PACKAGING METHOD - The present invention relates to a semiconductor packaging method. The method comprises (S | 02-26-2009 |
| 20090091044 | DICING DIE ATTACHMENT FILM AND METHOD FOR PACKAGING SEMICONDUCTOR USING SAME - A dicing die attachment film includes a die attachment layer attached to one surface of a semiconductor wafer; a dicing film layer attached to a dicing die that is used for cutting the semi-conductor wafer into die units; and an intermediate layer laminated between the die attachment layer and the dicing film layer. The intermediate layer has a modulus of 100 to 3000 MPa, which is greater than a modulus of the die attachment layer and the dicing film layer. | 04-09-2009 |
| 20100087067 | METHOD FOR PACKAGING SEMICONDUCTOR - A method for packaging a semiconductor is provided to allow uniform coating of a die attachment paste, shorten a B-staging time, and improve die pick-up characteristics and die attachment characteristics. This method includes preparing a die attachment paste with a viscosity of 1,500 to 100,000 cps; rotating a wafer and applying the die attachment paste to an upper surface of the wafer into a predetermined thickness; and B-staging the paste applied on the wafer. This method makes it possible to reduce costs by substituting for WBL (Wafer Backside Lamination) film, uniformly apply a die attachment paste to a wafer, freely control a thickness of applied die attachment paste by adjusting viscosity and dosage of discharged paste and a speed of a spin coater, and also shorten a process time by decreasing a B-staging time. | 04-08-2010 |
| 20100317155 | MULTIFUNCTIONAL DIE ATTACHMENT FILM AND SEMICONDUCTOR PACKAGING USING THE SAME - A multifunctional die attachment film used in a semiconductor packaging process includes a first die attachment film attached to a surface of a wafer having fine circuit patterns and solder bump patterns and having a first adhesive strength; and a second die attachment film attached on the first die attachment film and having a second adhesive strength with a wafer, a die chip, PCB and a flexible board, and the multifunctional die attachment film serves as a backgrinding tape in a backgrinding process, and after the backgrinding process is completed, the multifunctional die attachment film is not removed, but is used to attach a die chip to a connection member. And, the present invention utilizes the die attachment film as a backgrinding tape in the backgrinding process and concurrently a wafer protection means in a wafer dicing process, thereby preventing sawing burr, scratches or cracks. | 12-16-2010 |
Yoo-Jeong Hyun, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090196622 | Reconnection method in peripheral interface using visible light communication - A reconnection method and device for a peripheral interface using VLC provide a protocol for when a communication link between a primary device and a secondary device is disconnected. The primary device generates an R-XID message including reconnection information and a warning indication signal indicating the disconnection. The secondary device aligns the communication link with the primary device using the warning indication signal, receives the R-XID message from the primary device by the secondary device, and transmits an R-XID response message for the R-XID message to the primary device. | 08-06-2009 |