Hyon-Chol
Hyon-Chol Kim, Hwaseong-Si KR
Patent application number | Description | Published |
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20110233771 | SEMICONDUCTOR PACKAGES HAVING WARPAGE COMPENSATION - A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package. | 09-29-2011 |
20120280404 | STACK PACKAGES HAVING FASTENING ELEMENT AND HALOGEN-FREE INTER-PACKAGE CONNECTOR - A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate. | 11-08-2012 |
20140077382 | SEMICONDUCTOR PACKAGES HAVING WARPAGE COMPENSATION - A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package. | 03-20-2014 |
20140335657 | STACK PACKAGES HAVING FASTENING ELEMENT AND HALOGEN-FREE INTER-PACKAGE CONNECTOR - A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate. | 11-13-2014 |
Hyon-Chol Kim, Hwasoong-Si KR
Patent application number | Description | Published |
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20120018871 | STACK PACKAGE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip. | 01-26-2012 |
Hyon-Chol Kim, Seoul KR
Patent application number | Description | Published |
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20140061841 | SEMICONDUCTOR PACKAGE - A semiconductor package including a substrate including an epoxy-based material, an image sensor chip mounted on the substrate, and an attaching part provided between the substrate and the image sensor chip may be provided. The attaching part may include a first attaching part, and a second attaching part provided around the first attaching part. The first attaching part may achieve high reliability of the semiconductor package in association with the second attaching part. The second attaching part may include a material having a low rigidity. Thus, it is possible to reduce or prevent warpage of the image sensor chip from occurring. Due to the presence of the second attaching part, a plane coverage ratio of the first attaching part relative to the image sensor chip can be reduced. Thus, the warpage of the image sensor chip can be reduced or prevented more effectively. | 03-06-2014 |
Hyon-Chol Lim, Guro-Gu KR
Patent application number | Description | Published |
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20100148251 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a substrate on and/or over which a first conductive type well is formed; and an LDMOS device that includes a gate electrode and has a drain region formed in the substrate. The LDMOS device includes a trench formed on the substrate, a second conductive type body that is formed on one side of the trench and on the substrate therebeneath, and a first conductive type source region that is formed in the second conductive type body. | 06-17-2010 |