| Patent application number | Description | Published |
|---|
| 20090167576 | METHOD OF STEPWISE ELIMINATING VOLTAGE OFFSET AND VOLTAGE OFFSET ELIMINATION DEVICE IN ANALOG TO DIGITAL PIPELINE CONVERTER - Disclosed is a device of stepwise eliminating an offset voltage in an analog-to-digital pipeline converter. The device includes a sub analog-to-digital converter to convert an input signal inputted from a preceding stage into a first digital signal, a sub digital-to-analog converter to convert the first digital signal into a first analog signal, and an offset removing unit to remove a part of the offset voltage according to an offset code relative to the offset voltage based on a remaining signal to thereby generate a corrected remaining signal. | 07-02-2009 |
| 20110156780 | APPARATUS FOR DETECTING JITTER OF PHASE LOCKED LOOP - A method and apparatus for detecting jitter of a Phase Locked Loop (PLL), which is capable of detecting a jitter level of the PLL without using a separate jitter measurement device, is disclosed. The apparatus for detecting the jitter of the PLL includes the PLL configured to detect a phase difference signal between a reference clock and a feedback clock and to generate an oscillation signal having a predetermined frequency according to the phase difference signal, a variable phase delay unit configured to switch a plurality of capacitors according to an input delay control signal and to delay the phase difference signal from the PLL according to the delay control signal, a comparator configured to compare the phase difference signal from the PLL with the phase difference signal delayed by the variable phase delay unit and to detect a delay period of the phase difference signal, and a lock detection unit configured to detect whether the oscillation signal is within a lock range after the delay period detected by the comparator. | 06-30-2011 |
| 20110157104 | DATA TRANSMITTING DEVICE AND FLAT PLATE DISPLAY USING THE SAME - A data transmitting device and a flat plate display using the same are disclosed. The data transmitting device includes a clock generator to generate and output a first clock signal and to generate a plurality of second clocks signals having different phases; a serializer to convert parallel image data and a dot clock input at a slow speed to high speed serial data and high speed clock according to the first and second clocks outputted from the clock generator and to output the high speed serial image data and the high speed clock; and a signal converter to convert the serial image data and the high speed clock outputted from the serializer into differential signals and to output the differential signals. | 06-30-2011 |
