| Patent application number | Description | Published |
|---|
| 20090166853 | MULTI-LAYER STACKED WAFER LEVEL SEMICONDUCTOR PACKAGE MODULE - A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad. | 07-02-2009 |
| 20090184414 | WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME - A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads. | 07-23-2009 |
| 20090197372 | METHOD FOR MANUFACTURING STACK PACKAGE USING THROUGH-ELECTRODES - Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level. | 08-06-2009 |
| 20110006412 | SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR MANUFACTURING THEREOF AND STACK PACKAGE USING THE SAME - A semiconductor chip package and method for manufacturing thereof and stack package using the same is presented that reduces electrical signal transmission delays and realizes a reduction in thickness is presented. The stack package includes a plurality of semiconductor chip packages coupled to a substrate. Each semiconductor chip package includes a substrate and a device layer attached to the substrate. The device layer has first bonding pads on a first surface and second bonding pads on a second surface opposite to the first surface. The first and second bonding pads are coupled together by through electrodes that pass through the device layer. The stack package also includes conductive materials attached to the second bonding pads such that the conductive materials couple together adjacent semiconductor chip packages and the substrate. | 01-13-2011 |
| Patent application number | Description | Published |
|---|
| 20090018803 | METHOD OF CLOTH SIMULATION USING LINEAR STRETCH/SHEAR MODEL - Deformations occurring in cloth can be decomposed into two components: the in-plane and the out-of-plane deformations. Stretch and shear are in-plane deformation, and bending is out-of-plane deformation. In the method, the numerical simulation can be done in real-time, and the models fix some flaws that existed in previous real-time models, leading to conspicuous reduction of artifacts. The (|x|−C) | 01-15-2009 |
| 20100057455 | Method and System for 3D Lip-Synch Generation with Data-Faithful Machine Learning - A method for generating three-dimensional speech animation is provided using data-driven and machine learning approaches. It utilizes the most relevant part of the captured utterances for the synthesis of input phoneme sequences. If highly relevant data are missing or lacking, then it utilizes less relevant (but more abundant) data and relies more heavily on machine learning for the lip-synch generation. | 03-04-2010 |
| 20100215235 | METHOD FOR POPULATION-DRIVEN IDENTIFICATION OF BODY LANDMARKS - A new method for the identification of body landmarks from three-dimensional (3D) human body scans without human intervention is provided. The method is based on a population in whom landmarks were identified and from whom 3D geometries were obtained. An unmarked body (subject) is landmarked if there is a landmarked body in the population whose geometry is similar to that of the subject. The similarity between the surface geometry of the subject and that of each individual in the population can be determined. A search is performed using the mesh registration technique to find a part-mesh with the least registration error; the landmarks of the best-matched result are then used for the subject. | 08-26-2010 |
| 20100250213 | SEMI-LAGRANGIAN CIP FLUID SOLVER WITHOUT DIMENSIONAL SPLITTING - A new constrained interpolation profile method, which is stable and accurate but requires less amount of computation, is provided. CIP is a high-order fluid advection solver that can reproduce rich details of fluids. It has third-order accuracy but its computation is performed over a compact stencil. A novel modification of the original CIP method that fixes all of the above problems without increasing the computational load or reducing the accuracy is provided. The proposed method brings significant improvements in both accuracy and speed. | 09-30-2010 |
| 20110112800 | Method for Simulating Stretching and Wiggling Liquids - A method for simulating the stretching and wiggling of liquids is provided. The complex phase-interface dynamics is effectively simulated by introducing the Eulerian vortex sheet method, which focuses on the vorticity at the interface and is extended to provide user control for the production of visual effects. The generated fluid flow creates complex surface details, such as thin and wiggling fluid sheets. To capture such high-frequency features efficiently, a denser grid is used for surface tracking in addition to coarser simulation grid. A filter, called the liquid-biased filter, is used to downsample the surface in the high-resolution grid into the coarse grid without unrealistic volume loss resulting from aliasing error. | 05-12-2011 |
