| Patent application number | Description | Published |
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| 20080238936 | METHOD AND APPARATUS FOR COMPENSATING FOR DISPLAY DEFECT OF FLAT PANEL DISPLAY - A method and apparatus for controlling picture quality of a flat panel display capable of electrically compensating for a display defect of a display panel are disclosed. The method of compensating for a display defect of a flat panel display includes reading identification information of a display panel; generating positional information indicating the position of the display defect and the form of the display defect of the display panel on the basis of first input information and the identification information; generating a compensation value for compensating the degree of the display defect of on the basis of second input information; storing the positional information and the compensation value in a memory; and reading the positional information and the compensation value from the memory, modulating data to be displayed at the position of the display defect of the display panel by the compensation value, and displaying the modulated data on the display panel. | 10-02-2008 |
| 20090102037 | SEMICONDUCTOR PACKAGE, MODULE, SYSTEM HAVING SOLDER BALL COUPLED TO CHIP PAD AND MANUFACTURING METHOD THEREOF - A semiconductor package structure having a solder ball coupled to a chip pad and a manufacturing method thereof, a semiconductor package module, and a system. A circuit board includes a through hole therein, and a conductor is formed on a sidewall of the through hole. A first semiconductor chip including a first chip pad is mounted on the circuit board. A solder ball is disposed in the through hole and is bonded to the conductor and the first chip pad. Therefore, an underfill can be removed from a semiconductor package, and thus, the semiconductor package can be reduced in thickness. | 04-23-2009 |
| 20090129144 | PHASE CHANGE MEMORY AND METHOD DISCHARGING BITLINE - Disclosed are a phase change memory device in which an active time is reduced and a method of discharging a bitline in the phase change memory device. In the phase change memory device having the reduced active time and the method of discharging the bitline in the phase change memory device, the bitline is either always discharged when the phase change memory device is in standby, is discharged after the active operation of the phase change memory device, or is discharged prior to and after the active operation of the phase change memory device. | 05-21-2009 |
| 20090141549 | Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith - At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer. | 06-04-2009 |
| 20090154221 | Non-Volatile memory device using variable resistance element with an improved write performance - A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first voltage, a sense amplifier supplied with the first voltage and reading data from the non-volatile memory cells selected from the memory cell array, and a write driver supplied with the external voltage and writing data to the non-volatile memory cells selected from the memory cell array. | 06-18-2009 |
| 20090161421 | PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS - A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data. | 06-25-2009 |
| 20090168494 | Semiconductor device having resistance based memory array, method of operation, and systems associated therewith - In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array. | 07-02-2009 |
| 20090296459 | Nonvolatile Memory Device Using Variable Resistive Element - A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level. | 12-03-2009 |
| 20090303243 | Circuit and method for compensating display defect in video display - Circuit for compensating a display defect in a video display device of the present invention includes a memory having position information on a plurality of regular patterned defective regions of a display panel, gray scale section information, a defect level data on each of the regular patterned defective regions, and a plurality of compensation data on each of the defect level data stored therein, a first compensation unit, upon reception of data to be displayed on the regular patterned defective regions, for determining defect level data on the regular patterned defective regions of the data to be displayed, selecting a compensation data set on the defect level data determined thus, and selecting a compensation data on the data to be displayed from the compensation data selected thus, for compensating the data to be displayed, and a second compensator for distributing the data compensated thus at the first compensation unit spatially and temporally by using dither patterns for making fine compensation, thereby suppressing size increase of the compensation data. | 12-10-2009 |
| 20090303807 | Semiconductor device and semiconductor system having the same - A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished. | 12-10-2009 |
| 20100008133 | PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS - A method of writing data in a phase change memory includes; receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells, sensing data stored in the selected phase change memory cell, determining whether or not the sensed data is equal to the write data, and if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications. | 01-14-2010 |
| 20100053185 | Video display device capable of compensating for display defects - A video display device including an integrated atypical/typical defect compensation circuit is disclosed. The video display device includes a display panel, a memory storing atypical/typical defect information used to compensate atypical/typical defect regions of the display panel, and an integrated atypical/typical compensation circuit including a first compensator for compensating input data to be displayed on the atypical/typical defect regions, using the atypical/typical defect information from the memory, and a second compensator for finely compensating the data compensated by the first compensator, using first and second dithering patterns. The compensation circuit supplies data to be displayed on normal regions, without compensation. The video display device also includes a timing controller including a dithering unit for finely compensating data output from the integrated atypical/typical compensation circuit, using a third dithering pattern different from the first and second dithering patterns, and a panel driver for driving the display panel under a control of the timing controller. | 03-04-2010 |
| 20100053204 | Method for setting compensation region for irregular deffect region in manage display device - The present invention relates to a method for setting a compensation region for an irregular defect region in an image display device, including the steps of detecting an irregular display defect, setting a horizontal width of the irregular defect region detected thus, generating a plurality of guide lines which divide the irregular defect region in a horizontal direction along the horizontal width set thus automatically, setting upper and lower side boundary lines to the irregular defect region at every interval of the plurality of the guide lines to generate a plurality of main compensation regions defined by the plurality of guide lines and the upper and lower side boundary lines, and generating a plurality of upper, lower, left, and right supplementary compensation regions at upper, lower, left, and right sides of the plurality of main compensation regions, which maintain a gap of each of the plurality of the guide lines, automatically. | 03-04-2010 |
| 20100061146 | Nonvolatile Memory Devices Including Variable Resistive Elements - A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents. | 03-11-2010 |
| 20100080039 | Nonvoltile memory device and method of driving the same - A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality of variable resistance memory cells; selectively connecting read global bit lines for reading data with the local bit lines, and firstly discharging the selectively connected local bit lines by turning on local bit line discharge transistors coupled to the read global bit lines; and selectively connecting write global bit lines for writing data with the local bit lines, and secondly discharging the selectively connected local bit lines by turning on global bit line discharge transistors. | 04-01-2010 |
| 20100091553 | SEMICONDUCTOR DEVICE HAVING RESISTANCE BASED MEMORY ARRAY AND METHOD OF OPERATION ASSOCIATED THEREWITH - In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array. | 04-15-2010 |
| 20100103726 | PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS - A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells. | 04-29-2010 |
| 20100124103 | Resistance-change random access memory device - A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations. | 05-20-2010 |
| 20100124105 | VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM - Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit. | 05-20-2010 |
| 20100128516 | Nonvolatile Memory Devices Having Bit Line Discharge Control Circuits Therein that Provide Equivalent Bit Line Discharge Control - A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of bit line selection circuits are also provided, which are responsive to bit line selection signals. A first plurality of bit line discharge circuits are electrically connected to respective ones of the first plurality of local bit lines. A bit line discharge control circuit is provided to drive the first plurality of bit line discharge circuits with equivalent bit line discharge signals during an operation to read data from a selected one of the first plurality of local bit lines. | 05-27-2010 |
| 20100214832 | PHASE-CHANGE RANDOM ACCESS MEMORY - A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal. | 08-26-2010 |
| 20100220521 | PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND RELATED METHODS OF OPERATION - A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command. | 09-02-2010 |
| 20100287635 | Cloned Canines and Method for Producing Thereof - Disclosed herein are a cloned canine and a production method thereof. The method comprises the steps of enucleating the oocyte of a canine to prepare an enucleated recipient oocyte, conducting nuclear transfer into the enucleated oocyte using a canine somatic cell as a nuclear donor cell under optimized conditions so as to prepare a nuclear transfer embryo, and transferring the nuclear transfer embryo into the oviduct of a surrogate mother. The present invention provides a method for producing cloned canines and thus, can contribute to the development of studies in veterinary medicine, anthropology and medical science such as the propagation of superior canines, the conservation of rare or nearly extinct canines, xenotransplantation and disease animal models. | 11-11-2010 |
| 20100329053 | SEMICONDUCTOR MEMORY DEVICE HAVING A REDUNDANCY AREA - Provided is a semiconductor memory device. The semiconductor memory includes a main area and a redundancy area. The main area includes a plurality of memory blocks sharing a write bit line and a read bit line. The redundancy area includes a plurality of redundancy memory blocks sharing a redundancy write bit line and a redundancy read bit line. The redundancy area is provided to replace a component in the main area having a defect. | 12-30-2010 |
| 20110032377 | DIGITAL PHOTOGRAPHING APPARATUS, METHOD OF CONTROLLING THE SAME, AND RECORDING MEDIUM STORING PROGRAM TO EXECUTE THE METHOD - Provided are a digital photographing apparatus capable of taking a self-shot, a method of controlling the same, and a recording medium storing a program to execute the method. A digital photographing apparatus includes a shooting unit, configured to generate a live image of a subject; a main display unit, configured to display the generated image; an auxiliary display unit mounted on a front of the digital photographing apparatus and configured to display the generated image; a determination unit configured to determine whether the auxiliary display unit is switched on or off; and a self-shot setting unit configured to set a self-shot mode when the auxiliary display unit is switched from an ‘off’ state to an ‘on’ state. | 02-10-2011 |
| 20110032406 | DIGITAL PHOTOGRAPHING APPARATUS, METHOD OF CONTROLLING THE SAME, AND COMPUTER-READABLE STORAGE MEDIUM - A method of controlling a digital photographing apparatus including a plurality of display units includes displaying a replay image file on a first display unit, determining whether additional information exists in the replay image file, searching for the additional information when the additional information exists in the replay image file, and displaying the additional information on a second display unit. | 02-10-2011 |
| 20110035665 | DIGITAL IMAGING PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME, AND RECORDING MEDIUM STORING PROGRAM TO EXECUTE THE METHOD - A digital image processing apparatus that includes a touch screen recognizing a touch input of a user, a method of controlling the digital image processing apparatus, and a recording medium storing a program for executing the method are provided. An embodiment of the digital image processing apparatus includes a touch screen recognizing a touch input of a user; a time calculator calculating a time of the touch input of the user; and a GUI generator generating a GUI corresponding to the calculated touch input time. | 02-10-2011 |
| 20110050953 | METHOD OF SETTING IMAGE ASPECT RATIO ACCORDING TO SCENE RECOGNITION AND DIGITAL PHOTOGRAPHING APPARATUS FOR PERFORMING THE METHOD - A method of setting a ratio of an input image according to scene recognition and a digital photographing apparatus for performing the method, the method including: generating an input image; recognizing a scene from the input image; and setting a ratio of the input image according to the recognized scene. A digital photographing apparatus that sets a ratio of an input image according to scene recognition, the apparatus including an image generating unit configured to generate an input image; a scene recognition unit configured to recognize a scene from the input image; and an image aspect ratio setting unit configured to set an aspect ratio of the input image according to the recognized scene. | 03-03-2011 |
| 20110063491 | DIGITAL PHOTOGRAPHING APPARATUS AND METHOD OF CONTROLLING THE SAME - A digital photographing apparatus and a method of controlling the digital photographing apparatus prevent a touch malfunction from occurring while holding the digital photographing apparatus by having a touch protection area in the digital photographing apparatus. The digital photographing apparatus includes a large-sized touch screen on one surface thereof, wherein the touch screen includes: a touch area which inputs a touch from a user and executes icons corresponding to the touch; and a touch protection area which is not activated by the touch when the touch from the user is input on the touch screen. | 03-17-2011 |
| 20110096611 | Semiconductor device and semiconductor system having the same - A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished. | 04-28-2011 |
| 20110110172 | Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith - At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer. | 05-12-2011 |
