Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Hye-Jin Cho
Hye-Jin Cho, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100117140 | NON-VOLATILE MEMORY DEVICE FOR 2-BIT OPERATION AND METHOD OF FABRICATING THE SAME - A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern. | 05-13-2010 |
| 20110086483 | NON-VOLATILE MEMORY DEVICE FOR 2-BIT OPERATION AND METHOD OF FABRICATING THE SAME - A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern. | 04-14-2011 |
Hye-Jin Cho, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090146291 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a semiconductor chip including a semiconductor substrate and a plurality of cell transistors arranged on the semiconductor substrate. Channel regions of the cell transistors have channel lengths that extend in a first direction, and the package further includes a supporting substrate having an upper surface on which the semiconductor chip is affixed. The supporting substrate is configured to bend in response to a temperature increase in a manner that applies a tensile stress to the channel regions of the semiconductor chip in the first direction. Related methods are also disclosed. | 06-11-2009 |
| 20090253243 | Methods of Manufacturing Non-Volatile Memory Devices - In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern. | 10-08-2009 |
| 20090315094 | Nonvolatile Memory Device - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string. | 12-24-2009 |
| 20100105181 | METHODS OF FABRICATING VERTICAL TWIN-CHANNEL TRANSISTORS - A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions. | 04-29-2010 |
Hye-Jin Cho, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090151781 | Solar cell having spherical surface and method of manufacturing the same - Provided is a solar cell having a spherical surface. The solar cell includes a substrate having a back contact layer formed thereon; a plurality of carbon nanoelectrodes formed on the back contact layer so as to cross the back contact layer at right angles; a p-type junction layer formed to have a plurality of spheres which surround the plurality of carbon nanoelectrodes; an n-type junction layer and a transparent electrode layer that are sequentially laminated on the p-type junction layer; a first electrode formed on one side of the top surface of the back contact layer; and a second electrode formed on one side of the top surface of the transparent layer. | 06-18-2009 |
| 20090286004 | METHOD OF FORMING PRINTED CIRCUIT PATTERN, FORMING GUIDE FOR PATTERN, AND GUIDE-FORMING INK - Disclosed are methods of forming a printed circuit pattern and forming a guide, and a guide-forming ink. The method of forming a printed circuit pattern in accordance with the present invention includes forming a guide by using guide-forming ink having a slip property, curing the formed guide by in-situ UV, and forming a printed circuit pattern on the inside of the cured guide by using metal ink. | 11-19-2009 |
| 20110117694 | SOLAR CELL HAVING SPHERICAL SURFACE AND METHOD OF MANUFACTURING THE SAME - Provided is a solar cell having a spherical surface. The solar cell includes a substrate having a back contact layer formed thereon; a plurality of carbon nanoelectrodes formed on the back contact layer so as to cross the back contact layer at right angles; a p-type junction layer formed to have a plurality of spheres which surround the plurality of carbon nanoelectrodes; an n-type junction layer and a transparent electrode layer that are sequentially laminated on the p-type junction layer; a first electrode formed on one side of the top surface of the back contact layer; and a second electrode formed on one side of the top surface of the transparent layer. | 05-19-2011 |
Hye-Jin Cho, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090223410 | METHOD FOR PRODUCING SILVER NANOPARTICLES AND CONDUCTIVE INK - A method of producing metal nanoparticles in a high yield rate and uniform shape and size, which is thus suitable for mass production. In addition, metal nanoparticles are provided that have superior dispersion stability when re-dispersed in various organic solvents, which thus suitable for use as a conductive ink having high conductivity. The method of producing nanoparticles includes mixing a metal precursor with a copper compound to a hydrocarbon based solvent, mixing an amine-based compound to the mixed solution of the metal precursor with copper compound and hydrocarbon based solvent, and mixing a compound including one or more atoms having at least one lone pair, selected from a group consisting of nitrogen, oxygen, sulfur and phosphorous to the mixed solution of the amine-based compound, metal precursor with a copper compound and hydrocarbon based solvent. | 09-10-2009 |