| Patent application number | Description | Published |
|---|
| 20090272702 | PROCESS AND APPARATUS FOR ONLINE REJUVENATION OF CONTAMINATED SULFOLANE SOLVENT - A continuous online process for rejuvenating whole stream of contaminated lean sulfolane in an extraction system is provided. In particular, a rejuvenator is installed in the solvent circulation loop to remove the contaminants continuously to keep the solvent clean, effective and less corrosive. Specifically, the rejuvenator comprises a high pressure vessel with a removable cover and a round rack with vertical stainless steel tubes fitted in the high pressure vessel. A magnetic bar is placed in each stainless steel tube. A screen cylinder is installed inside the ring of stainless steel tubes. As the contaminated sulfolane is passed through the rejuvenator, the rejuvenator picks up its contaminants. The rejuvenator can be dissembled to remove the contaminants periodically. The rejuvenator is characterized by simple in construction, reliable in operation, and low in operation and maintenance costs. With this rejuvenator, the extraction system can be operated at high efficiency and high capacity without the dreaded corrosion. | 11-05-2009 |
| 20100065504 | Novel filtration method for refining and chemical industries - A novel design of filters for removing iron rust particulates and other polymeric sludge from refinery and chemical process streams that are paramagnetic in nature is provided. The performance of these filters is greatly enhanced by the presence of the magnetic field induced by magnets. Basically, the filter comprises a high-pressure vessel with means to support the plurality of magnets in the form of bars or plates that are encased in stainless steel tubes or columns. Filters with various configurations are disclosed for accommodating the removal of contaminants from the process streams of different industries, with high efficiency for contaminants removal, simple construction, low operational and maintenance costs, and low hazardous operation. | 03-18-2010 |
| Patent application number | Description | Published |
|---|
| 20080232524 | JITTER-TOLERANCE-ENHANCED CDR USING A GDCO-BASED PHASE DETECTOR - An embodiment of a clock and data recovery circuit comprising a first clock and data recovery circuit with high bandwidth and a second clock and data recovery circuit with low bandwidth is disclosed. The first clock and data recovery circuit with high bandwidth receives a data signal and a reference signal to demux the data signal into a first signal and a second signal, wherein a second data rate X bps of the first signal and the second signal is half of a first data rate of the data signal. The second clock and data recovery circuit with low bandwidth receives and reduces jitter in the first signal and the second signal to output a first recovery signal and a second recovery signal. | 09-25-2008 |
| 20080260087 | MULTI-BAND BURST-MODE CLOCK AND DATA RECOVERY CIRCUIT - A clock and data recovery circuit is disclosed and comprises a first gated voltage-controlled oscillator, a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop. The first GVCO receives a data signal and a reference voltage to generate a first clock signal and a second clock signal based on the data signal. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the frequency of the first clock signal and the second clock signal at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second clock signal or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The double-edge-triggered D flip-flop comprises a data input terminal receiving the output signal from the matching circuit, a clock input terminal receiving the output signal from the multiplexer, and an output terminal outputting a recovered data signal. | 10-23-2008 |
| 20090195236 | SEMICONDUCTOR CIRCUITS CAPABLE OF MITIGATING UNWANTED EFFECTS CAUSED BY INPUT SIGNAL VARIATIONS - Semiconductor circuit capable of mitigating unwanted effects caused by variations in a received input signal are provided, in which a main circuit receives an input signal and comprises a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage. A replica circuit is coupled to the main circuit to duplicate a variation in a voltage at the first node caused by a variation in the input signal and dynamically adjusts the first bias voltage according to the duplicated variation such that the first current is maintained at a constant. | 08-06-2009 |
| 20100182056 | METHODS FOR CALIBRATING GATED OSCILLATOR AND OSCILLATOR CIRCUIT UTILIZING THE SAME - An oscillator circuit is provided. The oscillator circuit includes a gated oscillator and a calibration circuit. The gated oscillator is arranged to generate an oscillator signal according to a control signal, and receive a gating signal to align an edge of the oscillator signal with an edge of the gating signal. The calibration circuit coupled to the gated oscillator is arranged to receive a first clock signal and a second clock signal, detect an alignment operation of the gated oscillator according to the first clock signal and a second clock signal and generate the control signal according to the detected alignment operation. | 07-22-2010 |
| 20110068764 | Semiconductor Circuits Capable of Mitigating Unwanted Effects Caused by Input Signal Variations - Semiconductor circuit capable of mitigating unwanted effects caused by variations in a received input signal are provided, in which a main circuit receives an input signal and comprises a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage. A replica circuit is coupled to the main circuit to duplicate a variation in a voltage at the first node caused by a variation in the input signal and dynamically adjusts the first bias voltage according to the duplicated variation such that the first current is maintained at a constant. | 03-24-2011 |
