Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Hwang, NY
Charlie C. Hwang, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090033398 | Clock Distribution Network Wiring Structure - A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid. | 02-05-2009 |
| 20100001696 | SYSTEM TO IMPROVE A MULTISTAGE CHARGE PUMP AND ASSOCIATED METHODS - A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage. | 01-07-2010 |
| 20100001709 | SYSTEM TO GENERATE A REFERENCE FOR A CHARGE PUMP AND ASSOCIATED METHODS - A system to generate a reference for a charge pump may include a diode-connected transistor providing a reference voltage, and an output transistor. The system may also include a reference circuit to provide a current that is substantially temperature insensitive and the reference circuit delivers the current across the diode-connected transistor thereby enabling the reference voltage to move with processing of the diode-connected transistor. | 01-07-2010 |
| 20100002478 | SYSTEM TO IMPROVE A VOLTAGE MULTIPLIER AND ASSOCIATED METHODS - A system to improve a voltage multiplier may include a voltage multiplier circuit, and a capacitor carried by the multiplier circuit. The system may also include a transistor to charge an up voltage of the capacitor. | 01-07-2010 |
| 20110033017 | Method and Apparatus for Generating Synchronization Signals for Synchronizing Multiple Chips in a System - A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically. This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time. | 02-10-2011 |
Charlie C. Hwang, Wappingers Falls, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090027075 | System And Method of Digitally Testing An Analog Driver Circuit - A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal. The method of the present invention comprises digitally testing the differential driver circuit by activating a test enable signal, skewing the differential output termination impedance in response to the test enable signal, adjusting a voltage offset of the differential receiver circuit in response to the test enable signal, selecting a power level for the differential driver circuit in response to the test enable signal, enabling a decoder in response to the test enable signal, wherein the decoder activates only one segment of the differential driver circuit during any one test sequence, activating one of the segments for testing, stimulating the differential driver circuit with digital test patterns, receiving an output of the differential driver circuit by the differential receiver circuit, converting the received differential driver output to a single-ended signal, observing the single-ended signal; and deactivating the test enable signal. | 01-29-2009 |
Charlie Chornglii Hwang, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090237134 | MINIMIZING CLOCK UNCERTAINTY ON CLOCK DISTRIBUTION NETWORKS USING A MULTI-LEVEL DE-SKEWING TECHNIQUE - Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction. | 09-24-2009 |
Charlie Chornglii Hwang, Wappingers Falls, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090210840 | Optimization Method of Integrated Circuit Design for Reduction of Global Clock Load and Balancing Clock Skew - A design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks. The clustering of latch distribution tree components is combined with repositioning of such components within clock sector areas. The movement and clustering of components is such that the timing constraints are preserved. The methods is described in terms of reducing and balancing the load inside each clock sector, although the techniques may also be applied to balancing load between clock sectors. | 08-20-2009 |
Cheng S. Hwang, New Milford, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110110879 | Compositions and Methods for Enhancing Eyelashes - Cosmetic compositions comprising creatine and low amounts of a biotinylated tripeptide are disclosed, as well as methods of using such compositions to improve the appearance of eyelashes. These compositions are believed to have synergistic modulatory activities in a number of biochemical pathways implicated in lash health. | 05-12-2011 |
Emily M. Hwang, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090118851 | FACTORY LEVEL AND TOOL LEVEL ADVANCED PROCESS CONTROL SYSTEMS INTEGRATION IMPLEMENTATION - Integration of factory level advanced process control (FL-APC) system and tool level advanced process control (TL-APC) system using selectable APC operation modes indicating different operational settings for the FL-APC system and at least one TL-APC system is disclosed. During operation, the FL-APC system controls operation of the TL-APC system. The invention allows a manufacturing execution system (MES) to have additional capability to run the process control functions at FL-APC system and/or TL-APC system, and allows integration of a variety of different tools with a TL-APC system. An implementation method, system and program product are also disclosed. | 05-07-2009 |
Francis N. Hwang, New York, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090243833 | MONITORING SYSTEM AND METHOD FOR PATIENT CARE - A patient care monitoring system and method employ active RFID devices integrated with digital processing, memory and timing circuitry for patient identification, care giver identification and for identification of each prescribed treatment, procedure, medication and general and/or special care action. At the point-of-care, each care action identity device will match directly with the targeted patient identity device or issue an error warning to prevent mistakes. The patient identity device will also interact with an associated sensor network to proactively prompt care givers to provide general care actions, such as altering a patient's laying position, changing bed pan/clothing/bed sheet, etc. for invalid patients. Also the patient identity tag will furnish periodic records of every care action, mistakes, remedies, care givers' identities and time and date for a central processor of a healthcare facility to monitor the quality of patient care. Such record can also be potentially accessed via the Internet by the responsible regulatory agencies, accreditation associations, insurance firms and even patients' families to ensure patient care is meeting the standards as well as medical billing accuracy. | 10-01-2009 |
Hong-Sik Hwang, Clinton, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110273847 | ALLOY COMPOSITIONS AND TECHNIQUES FOR REDUCING INTERMETALLIC COMPOUND THICKNESSES AND OXIDATION OF METALS AND ALLOYS - Alloy compositions and techniques for reducing IMC thickness and oxidation of metals and alloys are disclosed. In one particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy or mixture consisting essentially of from about 90% to about 99.999% by weight indium and from about 0.001% to about 10% by weight germanium and unavoidable impurities. In another particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy consisting essentially of from about 90% to about 99.999% by weight gallium and from about 0.001% to about 10% by weight germanium and unavoidable impurities. | 11-10-2011 |
Jennifer Hwang, Penfield, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090017389 | Imaging member - The presently disclosed embodiments are directed to charge transport layers useful in electrostatography. More particularly, the embodiments pertain to an improved electrostatographic imaging member having a specific photoreceptor material package comprising a thick conductive undercoat layer, a charge generation layer, a long life charge transport layer, and an optional overcoat layer. | 01-15-2009 |
Jennifer Y. Hwang, Penfield, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090214978 | PHOTORECEPTOR MEMBER - An electrophotographic photoreceptor and method for forming a photoreceptor is disclosed which is provided with an anticorrosion layer on the interface between the supporting substrate surface and the undercoat layer. The photoreceptor has a high mechanical strength and minimizes defects in print for longer periods of time. | 08-27-2009 |
Jeonghyun Hwang, Ithaca, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090165816 | HIGHLY DOPED III-NITRIDE SEMICONDUCTORS - A method of forming a highly doped layer of AlGaN, is practiced by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×10 | 07-02-2009 |
Jeremy C. Hwang, Great Neck, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090162878 | METHODS AND COMPOSITIONS FOR DETECTING AND QUANTIFYING SAPPB - The present invention provides methods (assays) for detecting and/or quantifying sAPPβ, a secreted β-secretase (BACE1) cleavage fragment of the β-amyloid precursor protein (APP), in a biological sample. One such method includes contacting a biological sample with a first antibody that selectively binds to a BACE1 cleavage site on sAPPβ and detecting the presence of the antibody. Also provided are compositions, including antibodies that selectively bind to the BACE1 cleavage site of sAPPβ. Kits containing such compositions are also provided. Methods of diagnosing a neurodegenerative disease, such as AD, using the methods and compositions of the present invention are further provided. Methods for identifying BACE1 modulators, candidate compounds that are BACE1 modulators, and methods for treating, preventing or ameliorating neurodegenerative disease, such as AD, using such compounds or pharmaceutical compositions containing such compounds are also provided. | 06-25-2009 |
| 20100221760 | METHODS AND COMPOSITIONS FOR DETECTING AND QUANTIFYING sAPPbeta - The present invention provides methods (assays) for detecting and/or quantifying sAPPβ, a secreted β-secretase (BACE1) cleavage fragment of the β-amyloid precursor protein (APP), in a biological sample. One such method includes contacting a biological sample with a first antibody that selectively binds to a BACE1 cleavage site on sAPPβ and detecting the presence of the antibody. Also provided are compositions, including antibodies that selectively bind to the BACE1 cleavage site of sAPPβ. Kits containing such compositions are also provided. Methods of diagnosing a neurodegenerative disease, such as AD, using the methods and compositions of the present invention are further provided. Methods for identifying BACE1 modulators, candidate compounds that are BACE1 modulators, and methods for treating, preventing or ameliorating neurodegenerative disease, such as AD, using such compounds or pharmaceutical compositions containing such compounds are also provided. | 09-02-2010 |
| 20110071124 | Compounds that Inhibit Production of sAPPB and AB and Uses Thereof - The present invention relates to compounds with activity as inhibitors of sAPPβ and Aβ production, and methods for treating, preventing, or ameliorating neurodegenerative diseases, such as Alzheimer's disease and pharmaceutical compositions containing such candidate compounds. | 03-24-2011 |
Jin Hyun Hwang, Clifton Park, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100175914 | PASSIVE ELECTRICAL DEVICES AND METHODS OF FABRICATING PASSIVE ELECTRICAL DEVICES - A thin laminate passive electrical device, such as, a capacitor, and a method of fabricating a thin laminate passive electrical device are provided. The passive electrical device includes two conductors, for example, copper foil conductors, separated by a dielectric having a first layer of a first material having a softening point temperature greater than a first temperature and a first layer of a second material having a softening point temperature less than the first temperature. The first temperature may be at least 150 degrees C. or higher. By providing a first layer having a higher softening point material, shorting across the conductors, that can be promoted by the fabrication process, is prevented. Methods of fabricating passive electrical devices are also disclosed. | 07-15-2010 |
Kai-Sing J. Hwang, Orchard Park, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090318783 | System and method of evaluating a subject with an ingestible capsule - A computerized method of analyzing measurements obtained from the gastrointestinal tract of subject comprising the steps of providing an ingestible capsule ( | 12-24-2009 |
Lesley Hwang, Chappaqua, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100029817 | Sulfur-containing silane, filled elastomeric compositions containing same and articles made therefrom - Sulfur-containing silane and its partially to substantially complete hydrolyzate(s) are useful as additives for filled elastomeric compositions for tires and other cured rubber articles. | 02-04-2010 |
| 20110021692 | Sulfur-Containing Silane, Filled Elastomeric Compositions Containing Same And Articles Made Therefrom - Sulfur-containing silanes described herein can serve as coupling agents for fillers in elastomer compositions used, for example, in tires, belts, hoses, shoe soles, seals, gaskets, and the like. The sulfur containing silanes advantageously reduce or eliminate the generation of volatile organic compounds (VOCs) during use. | 01-27-2011 |