| Patent application number | Description | Published |
|---|
| 20100320605 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern. | 12-23-2010 |
| 20110260226 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a gate formed over an active region of a semiconductor substrate, a first spacer formed at a sidewall of the gate, a first contact plug formed at a lower sidewall of the first spacer being coupled to the active region, a second spacer formed at a sidewall of the first spacer over the first contact plug, and a second contact plug formed over the first contact plug. | 10-27-2011 |
| 20120001333 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern. | 01-05-2012 |
| Patent application number | Description | Published |
|---|
| 20090146246 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure. | 06-11-2009 |
| 20090218604 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer. | 09-03-2009 |
| 20090218628 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes a NMOS transistor of a peripheral circuit region. The NMOS transistor is formed over a relaxed silicon germanium layer and a silicon layer to have a tensile strain structure, thereby increasing electron mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a first silicon layer connected to a first active region of a semiconductor substrate, a second silicon layer and a relaxed silicon germanium layer formed over the first silicon layer expected to be a NMOS region, and a NMOS gate formed over the second silicon layer. | 09-03-2009 |
| 20090218635 | Semiconductor Device and Method for Manufacturing the Same - A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance. The semiconductor device may include: a second active region including a silicon layer connected to a first active region of a semiconductor substrate; a gate formed over the second active region; a spacer formed on sidewalls of the gate; a source/drain region form at both sides of the spacer; and a metal silicide layer formed over the gate and the source/drain region | 09-03-2009 |
| 20100117041 | RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element. | 05-13-2010 |
| 20110012207 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer. | 01-20-2011 |
| 20120040506 | Method for Forming Semiconductor Device - A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance. The semiconductor device may include: a second active region including a silicon layer connected to a first active region of a semiconductor substrate; a gate formed over the second active region; a spacer formed on sidewalls of the gate; a source/drain region form at both sides of the spacer; and a metal silicide layer formed over the gate and the source/drain region. | 02-16-2012 |
