| Patent application number | Description | Published |
|---|
| 20080277785 | PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE AND METHOD OF THE SAME - A package structure for packaging at least one of a plurality of integrated circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of integrated circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of integrated circuit devices and on a sidewall of it. | 11-13-2008 |
| 20090267230 | PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE AND METHOD OF THE SAME - The present invention discloses a package structure for an integrated circuit device and method for manufacturing the same. The method includes providing a wafer with multiple integrated circuit devices; providing an extendable substrate having a first surface supporting the wafer; forming multiple anti-elongation layers on a second surface of the extendable substrate, the second surface being opposite to the first surface; forming multiple recesses in the wafer for separating the integrated circuit devices from each other; elongating the extendable substrate to enlarge the multiple recesses; and forming an insulating layer to fill the recesses and cover multiple integrated circuit devices. | 10-29-2009 |
| 20090294953 | INTEGRATED CIRCUIT PACKAGE MODULE AND METHOD OF THE SAME - The present invention discloses an integrated circuit module and method of manufacturing the same. The integrated circuit module includes a chip and a carrier supporting the chip. The carrier defines a front side and a back side, and the chip is disposed on the front side. The carrier includes a first insulating layer defining a first opening at the back side, a second insulating layer defining a second opening and a chip accommodation opening at the front side, and a patterned conductive layer sandwiched in between the first insulating layer and the second insulating layer. The patterned conductive layer is formed with an inner contacting portion exposed through the chip accommodation opening and an outer contacting portion exposed through the first opening and the second opening. The inner contacting portion is connected to the chip through the chip accommodation opening. The outer contacting portion is provided for electronically connecting an electronic device to the patterned conductive layer selectively at the front side through the second opening and at the back side through the first opening. | 12-03-2009 |
| 20100012963 | LIGHT EMITTING DIODE AND METHOD OF THE SAME - A light emitting diode and a method of the same are provided. The light emitting diode includes a substrate with a first region and a second region, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. The light emitting diode further includes a plurality of vias, a first metal layer, a second metal layer, and a patterned passivation layer interposed between the second semiconductor layer and the first metal layer. The plurality of vias are located in the first region and penetrate through the second semiconductor layer and the light-emitting layer to expose part of the first semiconductor layer. The first metal layer is located in the first region, and electrically contacted with the first semiconductor layer through the plurality of vias. The second metal layer is located in the second region, and electrically contacted with the second semiconductor layer and electrically insulated from the first metal layer. The patterned passivation layer is configured to electrically isolate the first metal layer from the second semiconductor layer and the light-emitting layer. | 01-21-2010 |
| 20100090707 | TEST MODULE FOR RADIO FREQUENCY IDENTIFICATION CHIPS AND METHOD OF THE SAME - A test module and method for radio frequency identification (RFID) chips are provided. The test module includes a test head having a chip carrier for carrying a RFID chip to be tested, the chip carrier having a first antenna electronically connecting the RFID chip. The module further includes a second antenna for communicating with the first antenna; and a base supporting the chip carrier and the second antenna. The test module further includes a test computer electronically connecting the second antenna, wherein the test computer evaluates functions of the RFID chip by way of the communications between the first antenna and the second antenna. | 04-15-2010 |
| 20100267204 | PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE AND METHOD OF THE SAME - A package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of intergraded circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of intergraded circuit devices and on a sidewall of it. | 10-21-2010 |
