Patent application number | Description | Published |
20090008630 | TUNNELING TRANSISTOR WITH BARRIER - The invention suggests a transistor ( | 01-08-2009 |
20090203214 | SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE OBTAINED BY SUCH A METHOD - The invention relates to a method of manufacturing a semiconductor device ( | 08-13-2009 |
20100155685 | ELECTRONIC COMPONENT, AND A METHOD OF MANUFACTURING AN ELECTRONIC COMPONENT - An electronic component ( | 06-24-2010 |
20120250401 | PHASE CHANGE MEMORY (PCM) ARCHITECTURE AND A METHOD FOR WRITING INTO PCM ARCHITECTURE - A phase change memory (PCM) architecture and a method for writing a PCM architecture are described. In one embodiment, a PCM architecture includes a PCM array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. The bit line driver circuits are connected to the PCM array and the electrical ground. Other embodiments are also described. | 10-04-2012 |
20130320400 | HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed. | 12-05-2013 |
20140167064 | GaN HEMTs AND GaN DIODES - A GaN hetereojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectric layer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot. | 06-19-2014 |