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Hung, Kaohsiung City
Chang-Ying Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100200974 | SEMICONDUCTOR PACKAGE STRUCTURE USING THE SAME - A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element. | 08-12-2010 |
Chi-Feng Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110039922 | 18beta-GLYCYRRHETINIC ACID DERIVATIVES AND SYNTHETIC METHOD THEREOF - The present invention provides a chemical compound having the structure being one selected from a group consisting of | 02-17-2011 |
Chih Cheng Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100007009 | SEMICONDUCTOR PACKAGE AND METHOD FOR PROCESSING AND BONDING A WIRE - A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion. | 01-14-2010 |
| 20100200969 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion. | 08-12-2010 |
| 20100200981 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor package, a chip is disposed on a carrier. An inert gas is run around one end of a line portion of a copper bonding wire while the end is being formed into a spherical portion. The spherical portion is bonded to a pad of the chip. The chip and the copper bonding wire are sealed and the carrier is covered by a molding compound. | 08-12-2010 |
Chih-Pin Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080218981 | PACKAGE STRUCTURE FOR CONNECTION WITH OUTPUT/INPUT MODULE - A package structure for connection with an output/input module is disclosed. The package structure can be applied to conventional multi-chip packages and system in packages. The package structure defines at least one insertion cavity that is vertically or horizontally disposed. By simply inserting an output/input module into the insertion cavity, an electrical connection can be established between the output/input module and the package structure. Accordingly, the package structure thus constructed can address the repairing, replacement and upgrading problems of electronic components encountered by a package structure that adopts the conventional soldering connection method. | 09-11-2008 |
| 20080273313 | Carrier with embedded component and method for fabricating the same - A carrier with embedded components comprises a substrate and at least one embedded component. The substrate has at least one slot and a first composite layer. The embedded component is disposed at the slot of the substrate. The first composite layer has a degassing structure, at least one first through hole and at least one first fastener, wherein the degassing structure corresponds to the slot, the first through hole exposes the embedded component, and the first fastener is formed at the first through hole and contacts the embedded component. According to the present invention, the degassing structure can smoothly discharge the hydrosphere existing within the carrier under high temperature circumstances and the first fastener is in contact with the embedded component, which increases the joint strength between the embedded component and the substrate. | 11-06-2008 |
| 20090194851 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element disposed adjacent to a periphery of the substrate unit; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of tile package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of a grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield. | 08-06-2009 |
| 20090194852 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) a grounding element disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface; (4) a package body disposed adjacent to the upper surface and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a lateral surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The grounding element corresponds to a remnant of a conductive bump, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield. | 08-06-2009 |
| 20100265009 | STACKED LC RESONATOR AND BANDPASS FILTER OF USING THE SAME - A stacked LC resonator includes a parallel-plate capacitor, a dielectric layer and a spiral inductor. The parallel-plate capacitor has a first metal layer, a second metal layer opposed to the first metal layer and a middle dielectric layer formed between the first and second metal layers. The dielectric layer is formed on the second metal layer of the parallel-plate capacitor. The spiral inductor is formed on the dielectric layer and electrically connected with the first and second metal layers of the parallel-plate capacitor. | 10-21-2010 |
Chih-Wei Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090010533 | METHOD AND APPARATUS FOR DISPLAYING AN ENCODED IMAGE - An apparatus for displaying an encoded image is disclosed. The apparatus comprises a display device and a decoding unit. The decoding unit acquires a Bit-Per-Pixel (BPP) value from an encoded image, acquires a bit stream from the encoded image, acquires multiple pixel data indices by segmenting the bit stream every lengths of the BPP value, acquires a pixel color value of each pixel data index by retrieving a palette comprising multiple unique pixel color values respectively labeled by the pixel data indices, and outputs the acquired pixel color values to the display device for display of the encoded image. | 01-08-2009 |
Chi-Lun Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090207062 | GAMMA REFERENCE VOLTAGES GENERATING CIRCUIT - A gamma reference voltages generating circuit is disclosed in the present invention. The gamma reference voltages generating circuit comprises a voltage provider, a plurality of first digital-to-analog converters and a plurality of second digital-to-analog converters. The voltage provider generates a plurality of first supply voltages and a plurality of second supply voltages according to a first gamma reference voltage. The first digital-to-analog converters are electrically coupled to the first supply voltages for generating a plurality of second gamma reference voltages. The second digital-to-analog converters are electrically coupled to the second supply voltages for generating a plurality of third gamma reference voltages. | 08-20-2009 |
Ching-Huang Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090240383 | AUTOMOBILE DETECTION AND CONTROL GATEWAY INTERFACE AND METHOD THEREOF - An automobile detection and control gateway interface and a method thereof are provided. The automobile detection and control gateway interface is connected with a controller area network (CAN) formed by a body control module (BCM) and body devices, and pre-stores a plurality of device diagnostic commands and status diagnostic data, so that the BCM performs corresponding actions on specific body devices according to the device diagnostic commands and capture status feedback data transmitted over the CAN by the body devices, and outputs the status diagnostic data matching with the status feedback data for determining the operation status of the body devices or for the externally connected device to acquire. All the device diagnostic commands are transferred through the BCM to avoid interfering with the operation of the CAN and control the external device connected to the BCM, so as to ensure all the body devices are under control. | 09-24-2009 |
Chun-Cheng Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110318835 | Implant Surface Treatment Method Having Tissues Integrated - The present disclosure uses different kinds of surface treatment processes on titanium-made dental implants. The growth and attachment conditions of bone cells (MC3T3-E), fibroblasts(NIH 3T3) and epidermal cells (XB-2) on the metal surface of titanium slices with different surface treatments are observed. Tetra-calcium phosphate is used to perform secondary sand-blasting process to clean up the metal surface and provide calcium ions for osteoblastoma physiology. Thus, by adjusting the cells adhesive and proliferative abilities, the success rate of the clinical applications in dental implant is improved. | 12-29-2011 |
Chung-Hsuang Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120247383 | DEVICE WITH MICROBUBBLE-INDUCED SUPERHYDROPHOBIC SURFACES FOR DRAG REDUCTION AND BIOFOULING PREVENTION AND DEVICE FOR BIOFOULING PREVENTION - A device with microbubble-induced superhydrophobic surfaces for drag reduction and biofouling prevention includes an anodic microporous plate, a cathodic microporous plate, and a DC power supply. The anodic microporous plate and the cathodic microporous plate are mounted to a hull surface of a ship. The DC power supply includes a positive pole electrically connected to the anodic microporous plate and a negative pole electrically connected to the cathodic microporous plate. Seawater is electrolyzed to generate hydrogen microbubbles adjacent to a surface of the cathodic microporous plate and to generate oxygen microbubbles adjacent to a surface of the anodic microporous plate, forming superhydrophobic surfaces on the surfaces of the anodic microporous plate and the cathodic microporous plate. Electric current flows through the anodic microporous plate and the cathodic microporous plate to prevent biofouling. | 10-04-2012 |
Fu-Chun Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120033688 | Single longitudinal mode fiber laser apparatus - The present invention provides a single frequency fiber laser apparatus. The fiber laser apparatus includes a Faraday rotator mirror. A piece of erbium doped fiber is inside the laser cavity. A wavelength selective coupler is connected to the erbium doped fiber. A pump source is coupled via the wavelength selective coupler. At least one sub-ring cavity component and/or an absorb component are inserted into the cavity for facilitating suppressing laser side modes to create a single longitudinal mode fiber laser. A partial reflectance fiber Bragg grating (FBG) is used as the front cavity end for this fiber laser. | 02-09-2012 |
Hsien-Chang Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120225248 | ARTIFICIAL LEATHER HAVING COMPOSITE FIBER AND METHOD FOR MAKING THE SAME - The present invention relates to an artificial leather having composite fibers and a method for making the same. The artificial leather includes a substrate and a flexible film. The substrate includes a plurality of composite fibers. Each composite fiber includes a first composition and a second composition. The first composition is a thermoplastic non-elastomer, and the second composition is a thermoplastic elastomer. The second composition accounts for 5% to 70% of the total weight of the composite fiber. The second composition at the intersecting points between the composite fibers is molten to form a flexible bonding point. | 09-06-2012 |
Jung-Chou Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120171507 | ELECTROLYTIC MACHINING METHOD AND SEMIFINISHED WORKPIECE BY THE ELECTROLYTIC MACHINING METHOD - The present invention relates to an electrolytic machining method. For increasing size precision of electrolytic machining method, a metallic mask layer is formed on the surface of a workpiece whose material has high conductivity or volume electrochemical equivalent, whereby the metallic mask layer can be used as a sacrificial layer of electrolytic machining and simultaneously protects the non-machining region of the workpiece so as to reduce lateral machining of the workpiece Consequently, the size precision of electrolytic machining is enhanced. In addition, the feasibility of electrolytically machining a miniature interval between two machined structures is increased as well. In addition, the present invention provides a semifinished electrolytic workpiece, comprising a workpiece and a metallic mask layer formed on the surface of the workpiece. The conductivity or volume electrochemical equivalent of the metallic mask layer is smaller than that of the workpiece. | 07-05-2012 |
Kuo-Hsiang Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120268478 | Method for Dithering in Display Panel and Associated Apparatus - A dithering method and associated apparatus is provided. The method synthesizes a dither pattern including a plurality of elements. At least two of the plurality of elements are of a same value, and at least two of the elements of the same value respectively associate with different driving polarities to prevent flickering. While sub-pixel data of a sub-pixel corresponds between two predetermined color levels of the sub-pixel, a color level displayed by the sub-pixel is determined from the two predetermined color levels according to a sum of the sub-pixel data and the element corresponding to the sub-pixel. | 10-25-2012 |
Kuo-Wei Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110304402 | DEVICE AND METHOD FOR LOCKING AND CALIBRATING FREQUENCY - A device and a method for locking and calibrating a frequency is provided for receiving a precise external clock frequency to lock an adjustable oscillator that controls an oscillation frequency to a predetermined frequency. The device comprises a process unit and a frequency adjusting unit. The process unit is provided for comparing the oscillation frequency with a precise frequency to generate a frequency difference and a calibration signal according to the frequency difference. The frequency adjusting unit generates a locking voltage according to the comparison result of the calibration signal and the internal oscillation frequency for locking the oscillation frequency of the external adjustable oscillator to the predetermined frequency, so that the adjustable oscillator still can output a precise oscillation frequency without requiring a precise oscillator. | 12-15-2011 |
| 20120225681 | Method of Providing a Vehicle with Communication Service and Micro Base Station Applied to Vehicle - A method of providing services to a vehicle and a micro base station applicable to a vehicle. The micro base station is disposed on the vehicle and is connected to the core network and the mobile communication device, either with different or the same wireless communication techniques. The mobile communication device is then enabled to communicate with the core network according to a connection relation between the first wireless communication technique and the core network. With the micro base station and the method of providing services to the vehicle, chances of performing a handshaking process between the communication device installed on the vehicle and the core network base station are greatly reduced, and the stability of signals received by the mobile communication device is highly improved. Therefore, the communication quality between the mobile communication device and the core network is enhanced. | 09-06-2012 |
Li-Hsiang Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100003288 | CpG DNA Adjuvant in Avian Vaccines - A CpG DNA adjuvant in avian vaccines is disclosed, which includes an immunostimulatory oligodeoxynucleotide (ODN) having a plurality of TCG tandem repeats at a 5′end, a poly-G structure at a 3′ end, and at least one unmethylated CpG motif with avian specific flanking sequences at two ends thereof between the 5′ end and the 3′ end. The CpG DNA adjuvant in avian vaccines is advantageous to carry out large-scale production, specifically enhance avian innate and adaptive immune responses, and the CpG DNA adjuvant is hardly to be digested by DNase due to its particular structures. | 01-07-2010 |
Tin-Hun Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080226845 | Polyamic acid-based composition and liquid crystal orienting film - A polyamic acid-based composition includes: a polyamic acid A prepared by a process including reacting an aromatic tetracarboxylic dianhydride and an aromatic diamine; and a polyamic acid B prepared by a process including reacting an aliphatic tetracarboxylic dianhydride, an aromatic diamine having a side chain, and a non-aromatic diamine. A liquid crystal orienting film is formed by a process including: preparing a mixture containing the aforesaid polyamic acid-based composition and a solvent; coating the mixture onto a substrate so as to form a film on the substrate; and heating the film so as to convert polyamic acid of the polyamic acid-based composition into polyamide. | 09-18-2008 |
| 20080281112 | Diamine and polyamic acid derived therefrom for liquid crystal orientation applications - A diamine includes a structure of formula (I), | 11-13-2008 |
Tseng-Tung Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120285442 | HEAT STORAGE DEVICE - A heat storage device is revealed. The heat storage device mainly includes a heat storage tank and a heat conduction unit. A part of the heat conduction unit is arranged in a receiving space of the heat storage tank. The receiving space is filled with heat storage material. The heat storage material can be sand and crushed stone, brick clay, cement, cinder, shell, etc. The heat storage material can also use material or waste easily got from local sources. The heat storage tank is a vacant container. Thus the cost of manufacturing and transportation is reduced. Moreover, the recycling of the material and waste reduces pollutants and improves the environment. | 11-15-2012 |
Tzu-Chien Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090299903 | Non-Cash Cash-on-Delivery Method and System - The present invention provides a method and system for non-cash cash-on-delivery. In the conventional process of the cash-on-delivery in logistics, a wireless communication apparatus is provided to read the information of the identification docket number and a non-cash payment tool, and the information is transported to the logistics server so as to accomplish the mechanism of the collecting-and-paying for another with a financial institution. | 12-03-2009 |
Tzu-Hsiang Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120056226 | CHIP PACKAGE - An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump. | 03-08-2012 |
| 20120181672 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening. | 07-19-2012 |
| 20120193786 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate. | 08-02-2012 |
Tzu-Li Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100332887 | STORAGE CONTROL DEVICE HAVING CONTROLLER OPERATED ACCORDING TO DETECTION SIGNAL DERIVED FROM MONITORING POWER SIGNAL AND RELATED METHOD THEREOF - One exemplary storage control device for a storage medium includes a controller and a voltage detector, where the controller controls data access of the storage medium, and the voltage detector monitors a power signal and asserts a detection signal to notify the controller when anomaly of the power signal is detected. Another exemplary storage control device for a storage medium includes a voltage detector and a controller, where the voltage detector monitors a power signal to generate a detection signal, and the controller controls data access of the storage medium. In addition, the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and enters a second operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range. | 12-30-2010 |
| 20120177146 | DETECTING CIRCUIT AND RELATED DETECTING METHOD - A detecting circuit includes: a first offset generating circuit arranged to apply a first offset to an input signal pair comprising a positive input signal and a negative input signal and accordingly generate a first output signal pair comprising a first positive output signal and a first negative output signal; and a first sampling circuit coupled to the first offset generating circuit, the first sampling circuit arranged to sample a difference in voltage between the first positive output signal and the first negative output signal to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair. | 07-12-2012 |
| 20130058389 | SIGNAL TRANSMITTER AND SIGNAL TRANSMITTING METHOD FOR TRANSMITTING SPECIFIC DATA BIT WITH DIFFERENT PREDETERMINED VOLTAGE LEVELS - An exemplary signal transmitter includes a checking circuit and a driving circuit. The checking circuit is arranged for checking a plurality of successive data bits to be transmitted and accordingly generating a checking result. The driving circuit is arranged for referring to the checking result and transmitting a specific data bit with a plurality of different predetermined voltage levels. An exemplary signal transmitting method includes: checking a plurality of successive data bits to be transmitted, and accordingly generating a checking result; and transmitting a specific data bit with a plurality of different predetermined voltage levels according to the checking result. | 03-07-2013 |
Wei-Mao Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090154040 | MEMORY CARD WITH ELECTROSTATIC DISCHARGE PROTECTION AND MANUFACTURING METHOD THEREOF - A memory card with electrostatic discharge (ESD) protection and a manufacturing method thereof are provided. The memory card includes a circuit board, a set of contacts, at least one chip and an ESD protection path. The signal paths of the board is not exposed at the edge of the circuit board. The ESD protection path for transmitting ESD current is disposed on the circuit board. Furthermore, a part of the ESD protection path extends to the edge of the circuit board. | 06-18-2009 |
Wen-Han Hung, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080220574 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed. | 09-11-2008 |
| 20080237734 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME - A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor. | 10-02-2008 |
| 20080242031 | METHOD FOR FABRICATING P-CHANNEL FIELD-EFFECT TRANSISTOR (FET) - A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region. | 10-02-2008 |
| 20090166625 | MOS DEVICE STRUCTURE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 07-02-2009 |
| 20090239347 | METHOD OF FORMING MOS DEVICE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 09-24-2009 |
| 20110097868 | METHOD FOR FABRICATING P-CHANNEL FIELD-EFFECT TRANSISTOR (FET) - A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region. | 04-28-2011 |
| 20110104864 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed. | 05-05-2011 |
| 20110156156 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress, and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/O MOS transistor and without not noly the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor. | 06-30-2011 |
| 20110254064 | SEMICONDUCTOR DEVICE WITH CARBON ATOMS IMPLANTED UNDER GATE STRUCTURE - An exemplary semiconductor device includes a substrate, a spacer, a metal silicide layer and carbon atoms. The substrate has a gate structure formed thereon. The spacer is formed on the sidewall of the gate structure. The spacer has a first side adjacent to the gate structure and a second side away from the gate structure. The metal silicide layer is formed on the substrate and adjacent to the second side of the spacer but away from the first side of the spacer. The carbon atoms are formed into the substrate and adjacent to the first side of the spacer but away from the second side of the spacer. | 10-20-2011 |
| 20120009745 | METHOD FOR FABRICATING FIELD-EFFECT TRANSISTOR - A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure. | 01-12-2012 |
| 20120045880 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate. | 02-23-2012 |
| 20120070948 | ADJUSTING METHOD OF CHANNEL STRESS - An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region. | 03-22-2012 |
| 20120086054 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor structure is disclosed. The semiconductor structure includes a gate structure disposed on a substrate, a source and a drain respectively disposed in the substrate at two sides of the gate structure, a source contact plug disposed above the source and electrically connected to the source and a drain contact plug disposed above the drain and electrically connected to the drain. The source contact plug and the drain contact plug have relatively asymmetric element properties. | 04-12-2012 |
| 20120196418 | METHOD OF FABRICATING TRANSISTORS - A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively. | 08-02-2012 |
| 20120199890 | TRANSISTOR STRUCTURE - A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer. | 08-09-2012 |
| 20120256276 | Metal Gate and Fabricating Method Thereof - A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O | 10-11-2012 |
| 20120289015 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH ENHANCED CHANNEL STRESS - A method for fabricating a semiconductor device with enhanced channel stress is provided. The method includes the following steps. Firstly, a substrate is provided. Then, at least one source/drain region and a channel are formed in the substrate. A dummy gate is formed over the channel. A contact structure is formed over the source/drain region. After the contact structure is formed, the dummy gate is removed to form a trench. | 11-15-2012 |
| 20120309158 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer. | 12-06-2012 |
| 20120319214 | STRUCTURE OF METAL GATE AND FABRICATION METHOD THEREOF - A method for fabricating a metal gate includes the following steps. First, a substrate having an interfacial dielectric layer above the substrate is provided. Then, a gate trench having a barrier layer is formed in the interfacial dielectric layer. A source layer is disposed above the barrier layer. Next, a process is performed to have at least one element in the source layer move into the barrier layer. Finally, the barrier layer is removed and a metal layer fills up the gate trench. | 12-20-2012 |
| 20120329259 | METHOD FOR FABRICATING METAL-OXIDE- SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed. | 12-27-2012 |
Ya-Jyuan Hung, Kaohsiung City TW
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| 20130009288 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process. | 01-10-2013 |
| 20130023098 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate. | 01-24-2013 |
Yi-Ling Hung, Kaohsiung City TW
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|---|---|---|
| 20100044708 | THIN FILM TRANSISTOR, PIXEL STRUCTURE AND FABRICATION METHODS THEREOF - A fabrication method of a thin film transistor includes providing a substrate at first. Thereafter, a first gate is formed on the substrate. An insulator is then formed to cover the first gate and a portion of the substrate. After that, a channel structure is formed on the insulator above the first gate. In addition, a metal layer is formed to cover the channel structure and a portion of the insulator. Next, the metal layer is patterned, and at least the metal layer on two sidewalls of the channel structure is retained to form a source and a drain, respectively. Moreover, a passivation layer is formed to at least cover the source, the drain and a portion of the insulator. | 02-25-2010 |
Yin-Po Hung, Kaohsiung City TW
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|---|---|---|
| 20120091581 | PACKAGE UNIT AND STACKING STRUCTURE THEREOF - A package unit and a stacking structure thereof are provided. The package unit includes a substrate, a first patterned circuit layer, a first conductive pillar, a semiconductor element, an insulation layer, a second conductive pillar, a third conductive pillar, a second patterned circuit layer and a conductive bump. The first patterned circuit layer is disposed on a surface of the substrate. The first conductive pillar is deposited through the substrate. The semiconductor element is disposed on the substrate. The insulation layer covers the semiconductor element and the substrate. The second conductive pillar is deposited through the insulation layer. The third conductive pillar is deposited through the insulation layer. The second patterned circuit layer is disposed on the insulation layer. The conductive bump is disposed on the second patterned metal layer. | 04-19-2012 |
| 20130043599 | CHIP PACKAGE PROCESS AND CHIP PACKAGE STRUCTURE - Chip package processes and chip package structures are provided. The chip package structure includes a substrate, a chip, an insulating layer, a third patterned conductive layer and an electronic element. The substrate has a first patterned conductive layer. The chip is disposed on the substrate. A second patterned conductive layer of the chip is bonded to the first patterned conductive layer of the substrate. The chip has a first through hole. The insulating layer is disposed on the chip and filled into the first through hole. The insulating layer has a second through hole which passes through the first through hole. The third patterned conductive layer is disposed on the insulating layer and filled into the second through hole to electrically connect to the first patterned conductive layer. The electronic element is disposed on the third patterned conductive layer and electrically connects to the third patterned conductive layer. | 02-21-2013 |
Yung-Chang Hung, Kaohsiung City TW
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| 20120302142 | POLISHING PAD AND METHOD OF PRODUCING THE SAME - The present invention mainly relates to a polishing pad and method of producing the same. The polishing pad comprises a base material having a surface for polishing a substrate, wherein the surface comprises a plurality of bundles of first long fibers and an elastomer embedded into the bundles. The bundles of first long fibers are entangled with each other. | 11-29-2012 |
Yu-Pu Hung, Kaohsiung City TW
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|---|---|---|
| 20130099541 | CHAIR STRUCTURE - A chair structure has assembly portions provided on its seat for assembling with upper ends of chair legs. Button holes and a latch block are respectively provided on each chair leg and the seat for correspondingly snap fit together. Additionally, mortise holes and tenons are also provided respectively on the seat and the chair legs so that they can joint firmly together after the assembly of the seat and the chair legs. Thus, in addition to the engagement between the latch blocks and corresponding button holes, the joint strength between the seat and the chair legs can be further enhanced by the complementary fixing achieved by the joint action between the tenons and mortise holes. | 04-25-2013 |