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| 20080203553 | Stackable bare-die package - A stackable bare-die package primarily comprises a substrate, a chip, a plurality of bonding wires and an encapsulant. The substrate has a slot where a step is formed inside the slot where a plurality of inner fingers are disposed on the step. A plurality of outer pads are disposed on the bottom surface and a plurality of transfer pads on the top surface. The chip is disposed on the top surface and is electrically connected to the inner fingers by a plurality of bonding wires passing through the slot. An encapsulant is formed inside the slot to encapsulate the bonding wires. There is a height difference between the step and the bottom surface so that the loop height of the bonding wires will not exceed the bottom surface. Therefore, when stacking the stackable bare-die packages, the exposed back surface of the chip will not be touched nor stressed to avoid die crack issues. | 08-28-2008 |
| 20080265389 | Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications - A substrate for multi-chip stacking and a multi-chip stack package utilizing the substrate and its applications are disclosed. The substrate comprises a first wire-bonding finger, a second wire-bonding finger, a trace configured for electrical transmission and a loop wiring on a same surface. The first wire-bonding finger and the second wire-bonding finger are adjacent each other and to a die-attaching area of the substrate. The loop wiring connects the first wire-bonding finger with the second wire-bonding finger in series and connected to the trace. The loop wiring can be selectively broken or not when at least two chips are stacked on the die-attaching area and electrically connected to the first and second wire-bonding fingers respectively. Accordingly, the chips can operate respectively and independently without mutual interference if one of the chips is fail. Moreover, there is merit to apply the multi-chip stack package utilizing the substrate because it can be repaired after molding and without removing any bonding wire during semiconductor packaging processes. | 10-30-2008 |
| 20100155937 | Wafer structure with conductive bumps and fabrication method thereof - A wafer structure with conductive bumps and fabrication method thereof are disclosed herein. Conductive bumps are later converted into conductive balls. A central area and a marginal area are defined on the wafer. To achieve heights among conductive balls formed on the wafer structure, the sizes (can be but not limited to one) of under bump metallurgy (UBM) layer blocks in the central area are smaller than that in the marginal area. The fabrication procedure for forming under bump metallurgy layer blocks of different size includes depositing a photoresist layer on the metallurgy layer and pattern the photoresist with a photomask of smaller opening area for the central area than for the marginal area, and removing the photoresist layer and the portion of metallurgy layer under the photoresist layer. | 06-24-2010 |
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| 20080203555 | Universal substrate and semiconductor device utilizing the substrate - A universal substrate and a semiconductor device utilizing the substrate are disclosed in the present invention. The universal substrate mainly comprises a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate. The fuses are connected with the bifurcate wirings in series. By the bifurcate wirings and the fuses, each of the inner pads is electrically connected to all of the outer pads to provide optional electrical disconnections therebetween. Accordingly, the universal substrate can be utilized for connecting chips having various serial arrangements of bonding pads without replacing or manufacturing another substrate. | 08-28-2008 |
| 20110133327 | SEMICONDUCTOR PACKAGE OF METAL POST SOLDER-CHIP CONNECTION - A semiconductor package with MPS-C2 configuration is revealed, primarily comprising a substrate and a chip. A plurality of leads covered by a solder mask having a rectangular slot disposed on the top surface of the substrate to expose parts of the leads. A plurality of metal pillars are disposed on the active surface of the chip. A patterned plating layer is partially formed on the exposed portions of the leads located inside the slot to form a plurality of plating-defined fingers. Therefore, the soldering area of the solder on the leads can be constrained without exceeding the patterned plating layer to avoid issue of excessive solder ability. | 06-09-2011 |
| 20110156238 | SEMICONDUCTOR PACKAGE HAVING CHIP USING COPPER PROCESS - A semiconductor package having chip using copper process is revealed. A chip using copper process is disposed on a substrate. The substrate has a core layer, a copper circuitry with connecting pads, a patterned diffusion barrier, and a solder mask. The copper circuitry is formed on the core layer. The patterned diffusion barrier has such a pattern identical to the one of the copper circuitry that an upper surface of the copper circuitry is completely covered. The substrate further has a bonding layer formed on a portion of the patterned diffusion barrier inside the solder mask's opening. Therefore, diffusion of copper ions from the copper circuitry of the substrate to the active surface of the chip can be avoided to prevent function failure of the chip. | 06-30-2011 |
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| 20090261427 | MOS P-N JUNCTION DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 10-22-2009 |
| 20090261428 | MOS P-N JUNCTION SCHOTTKY DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 10-22-2009 |
| 20100327288 | TRENCH SCHOTTKY DIODE AND METHOD FOR MANUFACTURING THE SAME - A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure. | 12-30-2010 |
| 20110084353 | TRENCH SCHOTTKY RECTIFIER DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage. | 04-14-2011 |
